LPC47S42X Datasheet, PDF (141/264 Pages) SMSC Corporation – ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS

The LPC47S42x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute
resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected
via bit[7] of the WDT_TIMEOUT register (LD8:CRF1.7). The WDT time-out value is set through the
WDT_VAL Configuration register. Setting the WDT_VAL register to 0x00 disables the WDT function (this
is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload
and begin counting down from the value loaded. When the WDT count value reaches zero the counter
stops and sets the Watchdog time-out status bit in the WDT_CTRL Configuration Register. Note:
Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by
the Host CPU.
There are three system events that can reset the WDT. These are a Keyboard Interrupt, a Mouse Interrupt
and I/O reads/writes to address 0x201 (an external Joystick Port). The effect on the WDT for each of
these system events may be individually enabled or disabled through bits in the WDT_CFG configuration
register. When a system event is enabled through the WDT_CFG register, the occurrence of that event
will cause the WDT to reload the value stored in WDT_VAL and reset the WDT time-out status bit if set. If
all three system events are disabled the WDT will inevitably time out.
The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out status
bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Configuration Register.
When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit.
The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force
WD Time-out) Configuration Register. Writing a "1" to this bit forces the WDT count value to zero and
sets bit 0 of the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing. See the
Runtime Registers section for a description on these registers.
SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47S42x implements a “group” nIO_SMI output pin. The System Management Interrupt is a
non-maskable interrupt with the highest priority level used for OS transparent power management. The
nSMI group interrupt output consists of the enabled interrupts from Super I/O Device Interrupts and
many of the GPIOs pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be
programmed to be active high or active low via the polarity bit in the GP27 register. The output buffer
type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP27 register. The
nIO_SMI pin function defaults to active low, open-drain output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 7. The nSMI
output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The
SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register
2.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or
(EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT
and IRQ_KINT) or (EN_SMBus and IRQ_SMBus) or (EN_RI1 and IRQ_RI1) or (EN_P12 and IRQ_P12)
or (EN_RI2 and IRQ_RI2)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit
respectively.
141