LPC47S42X Datasheet, PDF (121/264 Pages) SMSC Corporation – ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS

Routable IRQ to Serial IRQ Conversion Capability
IRQINx functions are on pins 61 (IRQINA), 62 (IRQINB), 40 (IRQINC) and 44 (IRQIND) and are muxed
onto the GPIO pins as inputs. The IRQINx pin’s IRQ time slot in the Serial IRQ stream is selected via a
4-bit control register for each IRQINx function. A value of 0000 disables the IRQ function. These pins
are implemented such that internal functions take precedence over the IRQIN pins, i.e. if the IRQIN
control register is set to 0x06 and the internal floppy is set to 0x06, the floppy alone will drive the Serial
IRQ stream in the IRQ6 time slot. See Configuration registers located at an offset 0xF4 and 0xF5 in
Logical Device A.
The internal IRQs that are used for the devices in the part are given precedence over the IRQs on the
GPIO pins. That is, if the IRQx is selected for an activated logical device in the part through register
0x70, and it is enabled for use (see description below), then if the same IRQx is programmed on its
associated GPIO pin, the external IRQx will be blocked from the serial IRQ frame. If however the IRQx
is selected for an activated logical device in the part through register 0x70, and it is NOT enabled for
use, then if the same IRQx is programmed on its associated GPIO pin, this external IRQ will go onto the
serial IRQ frame. If the logical device is not activated then the IRQx is not considered enabled.
Therefore, if an IRQ is selected for the logical device through register 0x70 and the logical device is
activated, then the enable bit for the device, if present, is used to control whether the internal IRQ or the
external IRQ on a GPIO is placed onto the serial stream. The following devices have an enable bit:
FDC, UART 1, UART2, the parallel port and the SMBus controller. See “Note A. Logical Device IRQ
and DMA Operation” in the “Configuration” section..
The following devices do not have an enable bit: keyboard, mouse, WDT. For these devices, the
interrupt is enabled as follows: programming an IRQ in register 0x70 of logical device 7 enables the
keyboard interrupt, programming an IRQ in register 0x72 of logical device 7 enables the mouse interrupt
and programming an interrupt in the WDT_CFG register enables the WDT interrupt. Note that the
logical device must also be activated for the interrupt to be enabled.
User Note: In order to use the ISA IRQs muxed onto the GPIO pins, the corresponding IRQ must not be
used for any of the devices in the LPC47S42x.
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