SKY72302-21 Datasheet, PDF (9/23 Pages) Skyworks Solutions Inc. – SKY72302-21: Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer

DATA SHEET • SKY72302-21 FREQUENCY SYNTHESIZER
Table 1. SKY72302-21 Register Map
Address (Hex)
Register (Note 1)
Length (Bits)
0
Main Divider Register
12
1
Main Dividend MSB Register
12
2
Main Dividend LSB Register
12
3
Auxiliary Divider Register
12
4
Auxiliary Dividend Register
12
5
Reference Frequency Dividers Register
12
6
Phase Detector/Charge Pump Control Register
12
7
Power Down/Multiplexer Output Select Control Register
12
8
Modulation Control Register
12
9
Modulation Data Register
12
—
Modulation Data Register (Note 2) — direct input
2 d length d 12 bits
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
Address (Bits)
4
4
4
4
4
4
4
4
4
4
0
When the sum of the dividend and modulation data lie outside this
range, the value of N_integer must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Modulation Using the SKY72300, SKY72301, and SKY72302-21
Dual Synthesizers/PLLs (document number 101349).
Register Descriptions
Table 1 lists the 10 16-bit registers that are used to program the
SKY72302-21. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power-up,
all registers are reset to 0x000 except registers at address 0x0
and 0x3, which are set to 0x006.
Main Synthesizer Registers
The Main Divider Register contains the integer portion closest to
the desired fractional-N (or the integer-N) value minus 32 for the
main synthesizer. This register, in conjunction with the Main
Dividend and MSB/LSB Registers (which control the fraction offset
from –0.5 to +0.5), allows selection of a precise frequency.
NOTE: The fixed divide-by-four divider upstream from the
programmable main divider must be taken into
consideration to determine the value to be programmed in
this register. For more information, refer to the Register
Programming section in this document.
As shown in Figure 6, the value to be loaded is:
x Main Synthesizer Divider Index = Nine-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB and LSB Registers control the fraction
part of the desired fractional-N value and allow an offset of –0.5
to + 0.5 to the main integer selected through the Main Divider
Register. As shown in Figures 7 and 8, the values to be loaded
are:
x Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
x Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs
of the 18-bit dividend for the main synthesizer.
The Main Dividend MSB and LSB Register values are 2's
complement format.
NOTE: When in 10-bit mode, the Main Dividend LSB Register is
not required.
Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest
to the desired fractional-N (or integer-N) value minus 32 for the
auxiliary synthesizer. This register, in conjunction with the
Auxiliary Dividend Register (which controls the fraction offset from
–0.5 to +0.5), allows selection of a precise frequency. As shown
in Figure 9, the value to be loaded is:
x Auxiliary Synthesizer Divider Index = nine-bit value for the
integer portion of the auxiliary synthesizer dividers. Valid values
for this register are from 6 to 505 (fractional-N) or from 0 to 511
(integer-N).
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
101216L • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 9, 2009
9