SKY72302-21 Datasheet, PDF (4/23 Pages) Skyworks Solutions Inc. – SKY72302-21: Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer

DATA SHEET • SKY72302-21 FREQUENCY SYNTHESIZER
Power Down
The SKY72302-21 supports a number of power-down modes
through the serial interface. For more information, see the
Register Descriptions section of this document.
Serial Interface Operation
The serial interface consists of three pins: Clock (pin 1), Data
(pin 27), and CS (pin 28). The Clock signal controls data on the
two serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
If the CS signal is brought to a high state before the 13^th Clock
edge, the bit stream is assumed to be modulation data samples.
In this case, it is assumed that no address bits are present and
that all the bits in the stream should be loaded into the
Modulation Data Register.
Register Programming
Register programming equations, described in this section, use
the following variables and constants:
N_fractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (F_ref) multiplying factor such that
the resulting frequency is equal to the desired VCO
frequency.
N_integer
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (F_ref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
N_reg
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the '6 modulator
is in 18-bit mode, and 1024 when the '6 modulator is
in 10-bit mode.
dividend
When in 18-bit mode, this is the 18-bit signed input
value to the '6 modulator, ranging from
–131072 to +131071 and providing 262144 steps,
each step equal to F_{div_ref}/2¹⁸ Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the '6 modulator, ranging from
–512 to +511 and providing 1024 steps, each step
equal to Fdiv_ref/2¹⁰ Hz.
F_VCO
Desired VCO frequency (either F_{vco_main} or F_{vco_aux}).
F_{div_ref}
Divided reference frequency presented to the phase
detector (either F_{ref_main} or F_{ref_aux}).
Clock
Data
X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
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September 9, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 101216L