AAT2556 Datasheet, PDF (18/27 Pages) Advanced Analogic Technologies – Battery Charger and Step-Down Converter for Portable Applications

DATA SHEET
AAT2556
Battery Charger and Step-Down Converter for Portable Applications
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
I_RMS = I_O ·
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for the
edges of pulsed current drawn by the step-down con-
verter. Low ESR/ESL X7R and X5R ceramic capacitors are
ideal for this function. To minimize stray inductance, the
capacitor should be placed as closely as possible to the IC.
This keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C3) can be
seen in the evaluation board layout in Figure 6.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic capacitor should be placed in parallel
with the low ESR, ESL bypass ceramic capacitor. This
dampens the high Q network and stabilizes the system.
Battery Charger Output Capacitor (C2)
The AAT2556 only requires a 1μF ceramic capacitor on
the BAT pin to maintain circuit stability. This value should
be increased to 10μF or more if the battery connection is
made any distance from the charger output. If the
AAT2556 is to be used in applications where the battery
can be removed from the charger, such as with desktop
charging cradles, an output capacitor greater than 10μF
may be required to prevent the device from cycling on
and off when no battery is present.
Step-Down Converter Output Capacitor (C4)
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7μF to
10μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple. For enhanced
transient response and low temperature operation appli-
cations, a 10μF (X5R, X7R) ceramic capacitor is recom-
mended to stabilize extreme pulsed load conditions.
The output voltage droop due to a load transient is dom-
inated by the capacitance of the ceramic output capacitor.
During a step increase in load current, the ceramic output
capacitor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The relationship of the output volt-
age droop during the three switching cycles to the output
capacitance can be estimated by:
C_OUT
=
3 · ΔI_LOAD
V_DROOP · F_S
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 4.7μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
The maximum output capacitor RMS ripple current is
given by:
I = _RMS(MAX)
1
2·
·
3
V_OUT · (V_IN(MAX) - V_OUT)
L · F_S · V_IN(MAX)
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
18
202177B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 19, 2013