SKY72302 Datasheet, PDF (15/21 Pages) Skyworks Solutions Inc. – Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer

DATA SHEET • SKY72302 FREQUENCY SYNTHESIZER
tape and reel format. For packaging details, refer to the Skyworks
Application Note, Tape and Reel, document number 101568.
Figure 16 provides a schematic diagram for the SKY72302.
Figure 17 shows the package dimensions for the 28-pin
EP-TSSOP and Figure 18 provides the tape and reel dimensions.
Electrical and Mechanical Specifications
The SKY72302 is supplied as a 28-pin EP-TSSOP. The exposed
pad is located on the bottom side of the package and must be
connected to ground for proper operation. The exposed pad
should be soldered directly to the circuit board.
Signal pin assignments and functional pin descriptions are
specified in Table 5. The absolute maximum ratings of the
SKY72302 are provided in Table 6. The recommended operating
conditions are specified in Table 7 and electrical specifications
are provided in Table 8.
Electrostatic Discharge (ESD) Sensitivity
The SKY72302 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper ESD
precautions.
Table 5. SKY72302 Signal Descriptions (1 of 2)
Pin #
Pin Name
Type
1
Clock
Digital input
2
Mod_in
3
Mux_out
Digital input
Digital output
4
VSUBdigital
–
5
GNDecl/cml (Note 1) Power and ground
6
VCCcml_main
(Note 1)
Power and ground
7
Fvco_main
Input
8
Fvco_main
Input
9
LD/PSmain
Analog output
10 VCCcp_main
(Note 1)
11 CPout_main
12 GNDcp_main
(Note 1)
13 Xtalacgnd/OSC
14 Xtalin/OSC
15 Xtalout/NC
16 VCCxtal
17 GNDxtal
18 LD/PSaux
Power and ground
Analog output
Power and ground
Ground/input
Input
Input
Power and ground
Power and ground
Analog output
19 VCCcp_aux (Note 1) Power and ground
Description
Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the
Data pin on the rising edge of Clock.
Alternate serial modulation data input pin. Address bits are followed by data bits.
Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main
or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be tri-stated from
the general synthesizer registers.
Substrate isolation. Connect to ground.
Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground.
ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump.
Main VCO differential input.
Main VCO complimentary differential input.
Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This
pin is configured using the Phase Detector/Charge Pump Control Register.
Main charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain
and charge pump.
Main charge pump output. The gain of the main charge pump phase detector is controlled by the Phase
Detector/Charge Pump Control Register.
Main charge pump ground.
Reference crystal AC ground or external oscillator differential input.
Reference crystal input or external oscillator differential input.
Reference crystal output or no connect.
Crystal oscillator ECL/CML, 3 V.
Crystal oscillator ground.
Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO.
This pin is configured using the Phase Detector/Charge Pump Control Register.
Auxiliary charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain
and charge pump.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
101216K • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • May 16, 2007
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