SKY65006-348LF Datasheet, PDF (13/15 Pages) Skyworks Solutions Inc. – 2.4-2.5 GHz WLAN/Zigbee Power Amplifier

Data Sheet • SKY65006-348LF
Although there is no need for external matching when operating
in a 50 Ω system, an input and output 6 pF decoupling capacitor
is shown on the evaluation circuit. This capacitor is only man-
datory on the RF output side of the device. The RF input is DC
isolated and could be connected to driver circuits directly without
the need for additional blocking capacitors. Capacitors of 5.6 pF
were chosen because their self-resonant frequency would not
add any unwanted disturbances in the 50 Ω transmission line
path. The SKY65006 is unconditionally stable at any frequency
and voltage setting as long as it is grounded correctly. It is
extremely important to pay special attention to the RF grounding
pad under the device. Ground pad vias and solder mask pat-
terns are designed in such a way to ensure minimum parasitic
inductance to the underlying ground and at each RF bypassing
component. To ensure reliable soldering of the device paddle, it
is highly recommended that filled vias with a minimal reliable
diameter and filling the entire pattern be used. The filled-via
technique would remove the possibility of solder migration down
via holes, which can cause a large increase in inductance and
possible instabilities.
Each amplifier stage is biased through a series choke and shunt
capacitor combination which is completely integrated on chip to
provide maximum RF isolation and harmonic radiation immunity.
To avoid interferences from the low-frequency gain of the ampli-
fier and to insure stability at low out of band frequencies, stage
1 amplifier is biased through inductor L₁. It is also then shunted
by a large value capacitance to ensure proper low-frequency
bypassing of the amplifier. To avoid a shunting effect on the
50 Ω line, a high-impedance, self-resonating choke L₂ (in the
range of 22–33 nH depending on vendor and size) and a large
value bypass capacitor are used for biasing the output stage.
Capacitor C₆, 4.7 µF, on the V_CC line should be placed as close
as possible to the biasing network supplying stage 2 or the
output stage of the amplifier. Applications with the DC bias being
generated strictly from a battery as the voltage source may not
require this capacitor, or as large a value as specified in the
applications circuit. However, in that case, a smaller ceramic
capacitor of at least 0.1 µF should be used and also placed
as close as possible to the biasing network supplying stage 2.
Capicator C₉ affects amplifier turn-on time. Reduce the
value of C₉ to decrease turn-on time as long as bias stability
is not compromised.
Note: Normal operation requires that V_CC including VBCC be
applied before the application of the V_REG voltages biasing stage
1 and 2 bias currents. If V_CC and VBCC are not applied prior to
the application of the V_REG biasing, voltage damage could occur
from excessive base current draw through the collector junction
of the bias transistor.
The SKY65006 also includes an on-board, compensated power
detector providing a single-ended output voltage for measuring
power over a wide dynamic range. The detector load and
settling time constant are set external to the device. Nominal
detector load is 51K Ω and 5 pF, yielding a settling time of
approximately 500 ns. Note that there is an internal 5 pF on-
chip capacitance, so the net capacitance value is approximately
10 pF. Lower resistor values may be used if necessary with
the net impact being a lower output detector voltage over its
useful dynamic range. For proper detector operation, a reference
voltage must be applied to the V_DET line. Any voltage between 2
and 4 V is acceptable for the reference voltage, but it is recom-
mended to supply V_DET from the V_REG power supply. The benefit
in doing
this is that the approximate 2 mA of current that the reference
circuit consumes will not be wasted with the PA in the “Off”
state. There is also the option of not biasing the detector refer-
ence if the current consumption is of prime importance, but the
detector will then act as a normal unbiased detector, and
sensitivity and accuracy will be degraded.
The evaluation circuit board is constructed as a four-layer FR4
stack with an overall thickness of 0.062 inches (1.57 mm). Top
layer dielectric is 0.01-inch thick with 50 Ω transmission line
widths of 0.0195 inches. The printed circuit board is constructed
using a symmetrical 0.01-inch stack on the top and bottom
layers and with a 0.032-inch thick pre-preg core. All components
are 0402 in size with the exception of the 4.7 µF and 10 µF tan-
talum capacitors. Please note the 10 µF capacitors are installed
to provide low frequency filtering for lab testing. Actual values,
if necessary, will be dependent upon layout and circuit environ-
ment. All ground vias used are 0.012 inches in diameter and
placed as close to the ground ends of by-passing components
as possible. Four vias are used under the device to create a low
inductance path to ground. If a smaller diameter is to be used, or
if the substrate thickness is greater than 0.01 inches, additional
vias must be placed under the device to reduce the potential risk
of parasitic oscillation.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
200122 Rev. H • Skyworks Proprietary Information. • Products and product information are subject to change without notice. • November 19, 2008
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