AAT1123 Datasheet, PDF (13/18 Pages) Advanced Analogic Technologies – 1MHz Step-Down Converter

DATA SHEET
AAT1123
1MHz Step-Down Converter
1
2
3
VIN
Enable
VOUT
C1
22μF
GND
R1 118k
L1
4.7μH
R2
59k
U1
AAT1123
1 _{EN PGND} 8
2 _{OUT PGND} 7
3 _{VIN PGND} 6
4 _{LX AGND} 5
C2
4.7μF
GND2
LX
U1 AAT1123 SC70JW-8
L1 CDRH3D16-4R7
C1 22μF 6.3V 0805 X5R
C2 4.7μF 6.3V 0805 X5R
Figure 5: AAT1123 Adjustable Evaluation Board Schematic.
Thermal Calculations
There are three types of losses associated with the
AAT1123 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
P_TOTAL
=
I_O2
·
(R_DSON(HS)
·
V_O
+ R_DSON(LS)
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term t_sw is used to estimate the full load step-down con-
verter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL = I_O2 · R_DSON(HS) + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the _JA for the SC70JW-8 pack-
age which is 160°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT1123 is shown in
Figures 2, 3, and 4. The following guidelines should be
used to help ensure a proper layout.
1. The input capacitor (C2) should connect as closely as
possible to V_IN (Pin 3) and PGND (Pins 6-8).
2. C1 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin should be as
short as possible.
3. The feedback trace or OUT pin (Pin 2) should be
separate from any power trace and connect as close-
ly as possible to the load point. Sensing along a
high-current load trace will degrade DC load regula-
tion. If external feedback resistors are used, they
should be placed as closely as possible to the OUT
pin (Pin 2) to minimize the length of the high imped-
ance feedback trace.
4. The resistance of the trace from the load return to
PGND (Pins 6-8) should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
201975B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 15, 2013
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