AAT1123 Datasheet, PDF (11/18 Pages) Advanced Analogic Technologies – 1MHz Step-Down Converter

for V_IN = 2 x V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT1123. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capaci-
DATA SHEET
AAT1123
1MHz Step-Down Converter
tor should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C2) can be
seen in the evaluation board layout in Figure 2.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Figure 2: AAT1123 Evaluation Board
Top Side.
Figure 3: Exploded View of Evaluation
Board Top Side Layout.
Figure 4: AAT1123 Evaluation Board
Bottom Side.
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