AAT2522 Datasheet, PDF (12/19 Pages) Skyworks Solutions Inc. – Dual High-Current, Low-Noise, Step-Down Regulator

DATA SHEET
AAT2522
Dual High-Current, Low-Noise, Step-Down Regulator
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The first-order relationship of the
output voltage droop during the three switching cycles to
the output capacitance can be estimated by:
C_OUT
=
3 · ΔI_O
V_DROOP · f_SW
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 10μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Input Capacitor Selection
Select a 10μF to 22μF X7R or X5R ceramic capacitor for
the input. To estimate the required input capacitor size,
determine the acceptable input ripple level (V_PK-PK) and
solve for C_IN. The calculated value varies with input volt-
age and is a maximum when V_IN is double the output
voltage (V_IN = 2x V_O):
C_IN =
D · (1 - D)
V_{PKPK - ESR}
I_O
· f_SW
and D =
V_O
V_IN
The peak ripple voltage occurs when V_IN = 2x V_O (50%
duty cycle), resulting in a minimum output capacitance
recommendation:
1
C_IN(MIN) =
V_{PKPK - ESR}
I_O
· 4 · f_SW
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the derated capacitance of a 10μF, 6.3V,
X5R ceramic capacitor with 5.0V DC applied is actually
about 6μF.
The maximum input capacitor RMS current is:
I_RMS = I_O · D · (1 - D)
I_RMS = I_O ·
V_{O · 1 -} V_O
V_IN
V_IN
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current:
I = _RMS(MAX)
I_O
2
occurs when V_IN = 2 · V_O
The term D (1-D) appears in both the input voltage rip-
ple and input capacitor RMS current equations and is a
maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2522. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1) can be
seen in the evaluation board layout in the Layout section
of this datasheet (see Figure 3).
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or
alu¬minum electrolytic should be placed in parallel with
the low ESR/ESL bypass ceramic capacitor. This damp-
ens the high Q network and stabilizes the system.
Adjustable Feedback Network
The output voltage on the AAT2522 is programmed with
external resistors R_OUT-FB and R_FB-GND. To limit the bias cur-
rent required for the external feedback resistor string
while maintaining good noise immunity. Although a
larger value will further reduce quiescent current, it will
also increase the impedance of the feedback node, mak-
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