AAT1282 Datasheet, PDF (12/22 Pages) Skyworks Solutions Inc. – 2A Driver for High Intensity LED Camera Flash

DATA SHEET
AAT1282
2A Driver for High Intensity LED Camera Flash
I²C Serial Interface
The AAT1282 is fully compliant with the industry-stan-
dard I²C interface. The I²C two-wire communications bus
consists of SDA and SCL lines. SDA provides data, while
SCL provides clock synchronization with speed up to
400kHz. SDA data transfers device address followed by
a register address and data bits sequence. When using
the I²C interface, EN is pulled high to enable the device
or low to disable the device. The I²C serial interface
requires a master to initiate all the communications with
target devices. The AAT1282 is a target device and only
supports the write protocol. The AAT1282 is manufac-
tured with a target device address of 0x37 (Hex). See
Figure 2 for the I²C interface diagram.
I²C START and STOP Conditions
START and STOP conditions are always generated by the
master. Prior to initiating a START, both the SDA and SCL
pins are in idle mode (idle mode is when there is no
activity on the bus and SDA and SCL are pulled high by
the external pull-up resistors). A START condition occurs
when the master strobes the SDA line low and after a
short period strobes the SCL line low. A START condition
acts as a signal to all ICs that transmission activity is
about to occur on the I²C bus. A STOP condition, as
shown in Figure 2, is when master releases the bus and
SCL changes from low to high followed by SDA low-to-
high transition. The master does not issue an
ACKNOWLEDGE and releases the SCL and SDA pins.
I²C Address Bit Map
Figure 4 illustrates the address bit transfer. The 7-bit
address is transferred with the Most Significant Bit (MSB)
first and is valid when SCL is high. This is followed by the
R/W bit in the Least Significant Bit (LSB) location. The
R/W bit on the eighth bit determines the direction of the
transfer (a '1' for read or a '0' for write). The AAT1282 is
a write-only device and the R/W bit must be set low. The
Acknowledge bit (ACK) is set to low by the AAT1282 to
acknowledge receipt of the address.
I²C Register Address/Data Bit Map
Figure 5 illustrates the Register Address or the serial data
bit transfer. The 8-bit data is always transferred most
significant bit first and is valid when SCL is high. The
Acknowledge bit (ACK) is set low by the AAT1282 to
acknowledge receipt of the register address or the data.
I²C Acknowledge Bit (ACK)
The Acknowledge bit is the ninth bit of each transfer on
the SDA line. It is used to send back a confirmation to
the master that the data has been received properly by
the target device. For each ACK to take place, the mas-
ter must first release the SDA line, and then the target
device will pull the SDA line low, as shown in Figures 1,
4, and 5.
ack from slave
ack from slave
start
MSB
Device Address LSB w
ack MSB Register Address LSB
ack
MSB
SCL
SDA
start
AAT1282 Device Address = 37h
w
ack
Register Address = 00h
ack
DATA
ack from slave
LSB
ack stop
Data = 06h
ack
stop
Figure 2: I²C Interface Diagram.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
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202305C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 20, 2013