ST8016S Datasheet, PDF (6/26 Pages) Sitronix Technology Co., Ltd. – COM/SEG LCD Driver

ST8016S
6. FUNCTIONAL DESCRIPTION
6.1
Pin Functions
(Segment mode)
SYMBOL
VDD
GND
LGND
VSS
V0L, V0R
V12L, V12R
V43L, V43R
DI7-DI0
XCK
LP
L/R
/DISPOFF
FR
MD
S/C
ElO1, EIO2
FUNCTION
Logic system power supply pin
Connected to +2.5 to +5.5 V.
Ground pin
Logic system power ground pin
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
Input pins for display data
In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be
connected to LGND or VDD.
In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins.
Refer to section 6.2.2.
Clock input pin for taking display data
Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
When set to LGND level "L", data is read sequentially from Y160 to Y1.
When set to VDD level "H", data is read sequentially from Y1 to Y160.
Refer to section 6.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y1-Y160) are set to level Vss.
When set to "L", the contents of the line latch are reset, but the display data are read in
the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled
the driver outputs non-select level (V12 or V43), then outputs the contents of the data
latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not
correspond to what is shown in AC characteristics, it cannot output the reading data
correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to LGND level "L", 4-bit parallel input mode is set.
When set to VDD level "H", 8-bit parallel input mode is set.
Refer to section 6.2.2.
Segment mode/common mode selection pin
When set to VDD level "H", segment mode is set.
Input/output pins for chip selection
When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input.
Preliminary Ver 0.24
Page 6/26
2009/10/01