ST8016S Datasheet, PDF (18/26 Pages) Sitronix Technology Co., Ltd. – COM/SEG LCD Driver

ST8016S
(Segment Mode 3) (LGND =VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+85 °C)
PARAMETER
SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
82
ns
1
Shift clock "H" pulse width
tWCKH
28
ns
Shift clock "L” pulse width
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise
tLD
0
ns
time
Shift clock fall to latch pulse fall
tSL
51
ns
time
Latch pulse rise to shift clock rise
tLS
30
ns
time
Latch pulse fall to shift clock fall
tLH
30
ns
time
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
57
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2 µs
Output delay time (3)
t PD3
CL = 15 pF
1.2 µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode) (LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +30.0 V, TOPR = -25 to +85° C)
PARAMETER
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNIT
Shift clock period
tWLP
tR,tF ≤ 20ns
250
ns
Shift clock "H" pulse width
tWLPH
VDD = +5.0± 0.5V
VDD = +2.5+ 4.5V
15
30
ns
ns
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tDL
CL = 15 pF
200
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
Preliminary Ver 0.24
Page 18/26
2009/10/01