SVG-2066 Datasheet, PDF (3/12 Pages) List of Unclassifed Manufacturers – 500MHz - 2200MHz 6-Bit Variable Gain Amp

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SVG-2066 500MHz-2200MHz 6-Bit VGA
Figure 1: Parallel Mode Timing Diagram (S-P=0) Table 2: Parallel Mode Truth table (S-P=0)
Attenuation State P0.5 P1
P2
P4
P8
P16
LE
Reference
0
0
0
0
0
0
0.5 dB
1
0
0
0
0
0
1 dB
0
1
0
0
0
0
Data
P0.5 thru
P16
2 dB
4 dB
8 dB
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
TD5
TD7
TD6
16 dB
31.5 dB
0
0
0
0
0
1
1
1
1
1
1
1
Table 1: Parallel Mode Timing Specifications (S-P=0)
Parameter
Symbol Unit Min Max
LE minimum pulse
width
TD6
nS
10
Delay set up time
before rising LE edge
TD5
nS
10
Data hold after falling
edge of LE
TD7
nS
10
Figure 2: Serial Mode Timing Diagram (S-P=1)
LE
CLK
DATA
MSB
16dB
8dB
4dB
2dB
TD1
TD2
LSB
1dB
0.5dB
TD3
TD4
Table 3: Serial Mode Timing Specifications
Parameter
Symbol Unit Min Max
Serial data delay before
clock rising edge
TD1
nS 10
Serial data hold after
clock falling edge
TD2
nS 10
LE delay after last clock
falling edge
TD3
nS 10
LE minimum pulse
width
TD4
nS 30
Serial data clock freq
FCLK MHz
20
Serial clock high time TCLKH nS 30
Serial clock low time
TCLKL nS 30
Table 4: Power Up Truth Table for Parallel Mode (S-P=0)
Attenuation State
LE
U1
U2
Reference
0
0
0
8 dB
0
1
0
16 dB
0
0
1
31 dB
0
1
1
Defined by P0.5 Thru P16
1
Not
Not
Applicable Applicable
Note: Serial mode power up (S-P=1) state is
defined by the parallel input logic shown in
Table 2.
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-104432 Rev 3