SVG-2066 Datasheet, PDF (2/12 Pages) List of Unclassifed Manufacturers – 500MHz - 2200MHz 6-Bit Variable Gain Amp

Advanced Information
SVG-2066 500MHz-2200MHz 6-Bit VGA
Specification continued
Symbol
Parameters: Test Conditions
Z₀ = 50Ω, V_CC = 5.0V,Vdd=3V Iq = 115mA
ERR Atten setting accuracy any state (500MHz-2200MHz)
DYNR Attenuation dynamic range
FCLK Serial Data Clock Frequency
VDD Drain voltage of Attenuator
IDD
Drain Supply Current
LH
Digital Logic High
LL
Digital Logic Low
ILEAK Digital Logic Leakage
Unit
dB
dB
MHz
V
uA
V
V
uA
Min.
30.3
2.7
0.7xVDD
0
Typ.
+/- 0.2
31.5
3.0
40
Max.
+/- (0.2+3% Atten setting)
32.7
20
3.3
100
VDD
0.3xVDD
1
Absolute Maximum Ratings
Parameters
MIn
Max
Unit
VCC Bias Current (I_C)
VCC Bias Voltage
220
mA
8
V
Power Dissipation
1.5
W
Drain Voltage (V_DD)
Voltage on any Digital Input
-0.3
4.0
V
-0.3
VDD+0.3
V
Operating Lead Temperature (T_L)
Max RF Input Power
-40
+85
ºC
21
dBm
Storage Temperature Range
-40
+150
ºC
Operating Junction Temperature (T_J)
ESD Human Body Model
+150
ºC
500
V
Operation of this device beyond any one of these limits may cause perma-
nent damage. For reliable continuous operation the device voltage and
current must not exceed the maximum operating values specified in the
table on page one.
Bias conditions should also satisfy the following expression:
I_DV_D < (T_J - T_L) / R_TH’ j-l
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Digital Interfacing:
Serial or Parallel Mode Selection
The SVG-2066 can be controlled with either a serial or parallel interface. The S-P bit selects the mode: S-P=low for parallel mode
and S-P=high for serial mode.
Parallel Mode Operation
For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load
data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram
and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly loaded
when the parallel line logic changes. The truth table for parallel operation is shown in Table 2.
Serial Mode Operation
Three CMOS compatible signals control the attenuator in this mode: DATA, CLK and LE. When LE is high the latch is enabled and
data in the serial shift register gets loaded. When the LE is low the data in the shift register is latched. Refer to Figure 2 for the tim-
ing diagram and Table 3 for the timing specifications.
Power up State Programming
At power up in serial mode the six control bits are set to the values available on the six parallel inputs P0.5 thru P16 (see Table 2).
For parallel mode the power up state is set with the two bit word defined by U1 and U2. See the truth table in Table 4.
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-104432 Rev 3