SLD-1000 Datasheet, PDF (3/5 Pages) SIRENZA MICRODEVICES – 4 Watt Discrete LDMOS FET-Bare Die

Impedance Data
Frequency (MHz)
880
960
1840
1960
2140
Z_source
2.7 + j 13.1
1.9 + j 10.6
1.7 + j 3.4
1.3 + j 2.0
1.2 + j 0.7
Z_load
12.5 + j 22.5
11.8 + j 18.3
1.0 + j 4.7
1.2 + j 5.7
1.7 + j 6.4
Impedances Referenced to Wirebond/PCB Interface.
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
De-embedding Information
Description
Gate
Number of Bond Wires
2
Length of Bond Wires
0.040
Height of Bond Wires
0.006
Pitch of Bond Wires
0.005
Bond Wire Diameter
0.002
Drain
3
0.040
0.006
0.005
0.002
All Dimensions in Inches.
Wirebond Heights Referenced to Top Surface of Die.
Input
Matching
Network
Device
under test
Zsource
Z _load
Output
Matching
Network
Z_source and Z_load are the optimal impedances presented to the SLD-1000 when operating at 28V, Idq=30mA, Pout=3.5 W PEP.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-104291 Rev C