SLD-1026Z Datasheet, PDF (2/21 Pages) SIRENZA MICRODEVICES – 3 Watt Discrete LDMOS Device Plastic Surface Mount Package

Preliminary
SLD-1026Z 3 Watt LDMOS FET
DC Specifications
Symbol
g_m
V_GS Threshold
V_GS Quiescent
V_DS Breakdown
C_iss
C_rss
C_oss
R_DSon
Parameter
Forward Transconductance @ 30mA I_DS
I_DS=3mA, V_DS=28V
I_DS=50mA, V_DS=28V
1mA V_DS current
Input Capacitance (Gate to Source) V_GS=0V V_DS=28V
Reverse Capacitance (Gate to Drain) V_GS=0V V_DS=28V
Output Capacitance (Drain to Source) V_GS=0V V_DS=28V
Drain to Source Resistance, V_GS=10V V_DS=250mV
Unit
Min
Typical
Max
mA / V
150
Volts
4.2
Volts
3
4
5
Volts
65
pF
5.2
pF
0.2
pF
3.2
Ω
3.0
Quality Specifications
Parameter
Description
ESD Rating
Human Body Model
Rating
1B
Pin Description
Pin #
Function
1, 3
NC
2
Gate
4, 6
5
GND
NC
Drain
Source, Gnd
Description
These pins are not connected internal to the package. Bus them to pin 2 as shown in the app circuit.
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant
bias current over the operating temperature range. Care must be taken to protect against video transients that exceed
the maximum input power or voltage.
These pins are not connected internal to the package. Bus them to pin 5 as shown in the app circuit.
Transistor RF output and drain bias voltage. Typical voltage 28V.
These pins are DC connected to the backside paddle. They provide good thermal connection to the backside paddle for
hand soldering and rework. Many thermal and electrical GND vias are recommended as shown in the landing pattern.
Pin Diagram
Absolute Maximum Ratings
GND
ESD
1
Protection
6
5
2
Parameters
Drain Voltage (V_DS )
Gate Voltage (V_GS)
RF Input Power
Load Impedance for Continuous Operation Without Damage
Output Device Channel Temperature
Value
35
20
+30
10:1
+150
Unit
Volts
Volts
dBm
VSWR
ºC
Operating Temperature Range
3
4
Storage Temperature Range
-40 to +85
ºC
-40 to +150
ºC
GND
Operation of this device beyond any one of these limits may cause permanent damage. For
reliable continuous operation see typical setup values specified in the table on page one.
Note 1:
Gate voltage must be applied to V_GS lead concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages
should never be applied to the transistor unless it is properly terminated on both input and output.
Note 2:
The required V_GS corresponding to a specific I_DQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS
transistors.
Note 3:
The threshold voltage (V_GSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza
application notes AN-067 LDMOS Bias Temperature Compensation.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
http://www.sirenza.com
EDS-104157 Rev F