SP690A Datasheet, PDF (9/16 Pages) Sipex Corporation – Low Power Microprocessor Supervisory with Battery Switch-Over

FEATURES
The SP690A/692A/802L/802M/805L/805M
provide four key functions:
1. A battery backup switching for CMOS RAM,
CMOS microprocessors, or other logic.
2. A reset output during power-up, power-down
and brownout conditions.
3. A reset pulse if the optional watchdog timer
has not been toggled within a specified time.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than +5V.
The parts differ in their reset-voltage threshold
levels and reset outputs. The SP690A/802L/
805L generate a reset when the supply voltage
drops below 4.65V. The SP692A/802M/805M
generate a reset below 4.40V.
The SP690A/692A/802L/802M/805L/805M
are ideally suited for applications in automotive
systems, intelligent instruments, and battery-
powered computers and controllers. All designs
into an environment where it is critical to
monitor the power supply to the µP and it’s
related digital components will find the
SSP690A/692A/802L/802M/805L/805M ideal.
Regulated +5V
VCC
0.1µF
µP ^{RESET RESET}
NMI
PFO
I/O LINE WDI
GND
VOUT
BUS
CMOS VCC
RAM
GND
Unregulated
DC
VCC
R1
PFI
R2
VBATT
GND
3.6V
Lithium
Battery
Figure 12. Typical Operating Circuit
THEORY OF OPERATION
The SP690A/692A/802L/802M/805L/805M
microprocessor (µP) supervisory circuits
monitor the power supplied to digital circuits
such as microprocessors, microcontrollers, or
memory. The series is an ideal solution for
portable, battery-powered equipment that
requires power supply monitoring. Implementing
this series will reduce the number of
components and overall complexity. The
watchdog functions of this product family will
continuously oversee the operational status of a
system. The operational features and benefits of
the SP690A/692A/802L/802M/805L/805M are
described in more detail below.
Reset Output
The microprocessor's (µP's) reset input starts
the µP in a known state. When the µP is in an
unknown state, it should be held in reset. The
SP690A/SP692A/SP802 assert reset during
power-up and prevent code execution errors
during power-down or brownout conditions.
On power-up, once V_CC reaches 1V, RESET is
guaranteed to be a logic low. As V_CC rises,
RESET remains low. When V_CC exceeds the
reset threshold, RESET will remain low for
200ms, Figure 9. If a brownout condition
occurs and V_CC dips below the reset threshold,
RESET is triggered. Each time RESET is
triggered, it stays low for the reset pulse width
interval. If a brownout condition interrupts a
previously initiated reset pulse, the reset pulse
continues for another 200ms. On power-down,
once V_CC goes below the threshold, RESET is
guaranteed to be logic low until V_CC drops
below 1V.
RESET is also triggered by a watchdog timeout.
If WDI remains either high or low for a period
that exceeds the watchdog timeout period (1.6
sec), RESET pulses low for 200mS. As long as
RESET is asserted, the watchdog timer remains
clear. When RESET comes high, the watchdog
resumes timing and must be serviced within
1.6sec. If WDI is tied high or low, a RESET
pulse is triggered every 1.8sec (t_WD plus t_RS).
SP690A/692ADS/08
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
9
© Copyright 2000 Sipex Corporation