SP6136 Datasheet, PDF (9/18 Pages) Sipex Corporation – Synchronous Buck Controller

APPLICATION INFORMATION
20V rated MOSFET is sufficient. For convert-
ers with 10-15Vin, as in the above example,
select a 30V MOSFET.
The calculation of Rds(on) for Top and Bottom
MOSFETs is interrelated and can be done
using the following procedure:
1) Calculate the maximum permissible
power dissipation P(dissipation) based on
required efficiency. The converter in the
above example should deliver an output
power Pout = 3.3V•10A = 33W. For a target
efficiency of 94%, input power Pin is given
by Pin = Pout/0.94 = 35.1W. Maximum al-
lowable power dissipation is then:
P(dissipation) = Pin – Pout = 2.1 W
2) Calculate the total power dissipation in
top and bottom MOSFETs P(_MOSFET) by sub-
tracting inductor losses from P(dissipation)
calculated in step 1. To simplify, disregard
core losses; then P_L = I²rms • DCR • 1.4,
where 1.4 accounts for the increase in DCR
at operating temperature. For the above
example P_L = 0.63W. Then:
P(_MOSFET) = 2.1W – 0.63W = 1.47W.
3) Calculate Rds(on) of the bottom MOSFET
by allocating 40% of calculated losses to it.
40% dissipation allocation reflects the fact
that the the top MOSFET has essentially no
switching loss. Then P(bottom) = 0.4X1.47W
= 0.59W. Rds(on) = P/(I²rms • 1.5) where Irms
= Iout • {1-(Vout/Vin)}^0.5 and 1.5 accounts
for the increase in Rds(on) at the operating
temperature. Then:
P
[ ] ^{Rds(on) =} {I²out • (1-Vout/Vin)} • 1.5
= 5.4 Ω.
4) Allocate 60% of the calculated losses
to the top MOSFET, P(top) = 0.6X1.47 =
0.88W. Assume conduction losses equal
to switching losses, then P = 0.5X0.88W =
0.44W. Since it operates at the duty cycle
of D=Vin/Vout; then:
Rds(on) =
= 10.7W.
P
[ ] I²out • (Vout/Vin) • 1.5
Gate-to-drain charge Qgd for the top MOS-
FET needs to be specified. A simplified
expression for switching losses is:
{ } Ps = Iout • Vin • f • Vin + Iout ...................(3)
dv/dt di/dt
where dv/dt and di/dt are the rates at which
voltage and current transition across the top
MOSFET respectively, and f is the switching
frequency. Voltage switching time (Vin _/dv/dt)
is related to Qgd:
(Vin _/dv/dt) = Qgd/ig............................... (4)
where ig is Current charging the gate-to-drain
capacitance. It can be calculated from:
ig = (Vdrive-Vgate)/Rdrive......................(5)
where Vdrive is the drive voltage of the
SP6136 top driver minus the drop across the
boost diode (approximately 4.5V); Vgate is
the top MOSFET’s gate voltage correspond-
ing to Iout (assume 2.5V) and Rdrive is the
internal resistance of the SP6136 top driver
(assume 2Ω average for turn-on and turn-off).
Substituting these values in equation (5) we
get ig = 1A. Substituting for ig in equation
(4), we get (Vin _/dv/dt) = Qgd. Substituting
for (Vin _/dv/dt) in equation (3) we have:
{ } Ps = Iout • Vin • f • Qgd + (Iout / di/dt)
Solving for Qgd we get:
{ ^{Qgd =}
Ps
} ^{_ Iout .............. (6)}
Iout • Vin • f
di/dt
Di/dt is usually limited by parasitic DC-Loop
Inductance (Lp) according to di/dt = Vin/Lp.
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller

© 2006 Sipex Corporation