SP6136 Datasheet, PDF (6/18 Pages) Sipex Corporation – Synchronous Buck Controller

The SP6136 contains two unique control
features that are very powerful in distributed
applications. First, non-synchronous driver
control is enabled during start up to prohibit
the low side NFET from pulling down the out-
put until the high side NFET has attempted to
turn on. Second, a 100% duty cycle timeout
ensures that the low side NFET is periodically
enhanced during extended periods at 100%
duty cycle. This guarantees the synchronized
refreshing of the BST capacitor during very
large duty ratios.
The SP6136 also contains a number of valu-
able protection features. A programmable
input UVLO allows a user to set the exact
value at which the conversion voltage is
at a safe point to begin down conversion,
and an internal V_CC UVLO ensures that
the controller itself has enough voltage to
properly operate. Other protection features
include thermal shutdown and short-circuit
detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP6136 is forced into an idle state where the
output drivers are held off for a finite period
before a re-start is attempted.
Soft Start
“Soft Start” is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter, ramping up the non-inverting input
of the error amplifier controls soft start. As a
result, excess source current can be defined
as the current required to charge the output
capacitor
IV_{IN, X} = ^{Cout • ΔVout}
∆TSoft-start
The SP6136 provides the user with the op-
tion to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
10µA pull up current present at the SS pin
THEORY OF OPERATION
and the 0.8V reference voltage. Therefore,
the excess current source can be redefined
as:
IV_{IN, X} = C_out • ΔV_out •

10µA
(Css X 0.8V)
Hiccup
Upon the detection of a power, thermal, or
short-circuit fault, the SP6136 is forced into
an idle state for a minimum of 200ms. The
SS and COMP pins are immediately pulled
low, and the gate drivers are held off for the
duration of the timeout period. Power and
thermal faults have to be removed before a
restart may be attempted, whereas, a short-
circuit fault is internally cleared shortly after
the fault latch is set. Therefore, a restart at-
tempt is guaranteed every 200ms (typical) as
long as the short-circuit condition persists.
A short-circuit detection comparator has
also been included in the SP6136 to protect
against the accidental short or severe build
up of current at the output of the power con-
verter. This comparator constantly monitors
the inputs to the error amplifier, and if the
V_FB pin ever falls more than 250mV (typical)
below the voltage reference, a short-circuit
fault is set. Because the SS pin overrides the
internal 0.8V reference during soft start, the
SP6136 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Error Amplifier & Voltage Loop
As stated before, the heart of the SP6136
voltage error loop is a high performance,
wide bandwidth transconductance ampli-
fier. Because of the amplifier’s current
limited (+100µA) transconductance, there
are many ways to compensate the voltage
loop or to control the COMP pin externally.
If a simple, single pole, single zero response
is required, then compensation can be as
simple as an RC circuit to ground. If a more
complex compensation is required, then the
amplifier has enough bandwidth (45° at 4
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller

© 2006 Sipex Corporation