SP6122 Datasheet, PDF (8/19 Pages) Sipex Corporation – Low Voltage, Micro 8, PFET, Buck Controller Ideal for 1A to 5A, Small Footprint, DC-DC Power Converters

Over Current Protection
Over current protection on the SP6122 is
implemented through detection of an ex-
cess voltage condition across the PFET
switch during conduction. This is typically
referred to as high side R_DS(ON) detection.
The over current comparator charges a
sampling capacitor each time V(I_SET) –
V(I_SENSE) exceeds 150mV (typ) and the
PDRV voltage is low. The discharge cur-
rent/charge current ratio on the sampling
capacitor is about 2%. Therefore, provided
that the over current condition persists, the
capacitor voltage will be pumped up during
each time PDRV switches low and this
voltage will trigger an over current condition
upon reaching a CMOS inverter threshold.
There are many advantages to this ap-
proach. First, the filtering action of the gated
S/H scheme protects against false trigger-
ing during a transient load condition or sup-
ply line noise. In addition, the total amount
of time to trigger the fault depends on the
on-time of the PFET switch. Ten, 1µs pulses
are equivalent to twenty, 500ns pulses or
one, 1µs pulse, however, depending on the
period, each scenario takes a different
amount of total time to trigger a fault. There-
fore, the fault becomes an indicator of aver-
age power in the PFET switch. Also, be-
cause the CMOS trip threshold is depen-
dent on V_CC, the over current scheme is
protected against false triggering due to
changes in line voltage.
Although the 150mV threshold is fixed, the
overall R_DS(ON) detection voltage can be
increased by placing a resistor from I_SET to
V_CC. A 20µA sink current programs the
additional voltage.
The 150 mV threshold and 20µA I_SET cur-
rent have 3800 ppm/°C and 4300 ppm/°C
temperature coefficients, respectively.
These TC’s are designed into the SP6122
in an effort to match the thermal character-
THEORY OF OPERATION: Continued
istics of the PFET switch. It assumed that
the SP6122 will be used in compact designs
where there is a high amount of thermal
coupling between the PFET and the con-
troller.
Light Load Operation
One of the advantages of the SP6122 mini-
mum on-time control scheme is the loop’s
ability to seamlessly and efficiently transi-
tion from heavy loads to light loads. In most
other control schemes, the controller is no-
tified about a light load condition and then
must abruptly change control schemes in
order to maintain efficiency. The SP6122
simply reduces the frequency when the
average load current is less than the aver-
age inductor ripple current. As a result,
switching loss decreases as the load cur-
rent decreases and overall efficiency is
maintained.
Output Driver
The driver stage consists of a high side, 4
ohm PFET driver. The following waveforms
illustrate basic behavior of the driver.
5V
90 %
PDRV
10 %
V(V_CC)
PDRV
Voltage
0V
V(V_CC) = V_IN
SWN
Voltage
0V
- V(V_DIODE)
Gate Driver Test Conditions
FALL TIME
RISE TIME
90 %
10 %
TIME
Rev. 7/16/03
SP6122 Low Voltage, Micro 8, PFET, Buck Controller
8
© Copyright 2003 Sipex Corporation