SP6122 Datasheet, PDF (6/19 Pages) Sipex Corporation – Low Voltage, Micro 8, PFET, Buck Controller Ideal for 1A to 5A, Small Footprint, DC-DC Power Converters

General Overview
The SP6122 is a minimum on-time, PFM
controller for low cost DC/DC step down
converters. The main control loop consists
of a REFERENCE COMPARATOR, an ON-
TIME CLOCK, a LOOP LATCH and a
BLANKING ONESHOT. The REFERENCE
comparator has 10mV of internal hysteresis
and a 1.25V internal reference. Both hyster-
esis and reference voltage are multiplied
upward by the internal feedback resistor
divider, K1 (K1 = 1 for the adjustable ver-
sion). This value is set by the factory and
determines the output voltage of the con-
verter. This divider is also used in the on-
time algorithm for the controller. If the out-
put voltage drops below K1*1.25V, then the
DRIVER LOGIC tells the PFET switch to be
“on” for a certain minimum time. The on-
time is set by the Soft Start CLOCK fre-
quency and is factory programmed to run at
300kHz. When the part is enabled, through
V_CC or the ENABLE pin, the DRIVER LOGIC
is configured to first look at the fixed fre-
quency Soft Start loop. The output voltage
is then controlled by a 0.5V/ms internal
ramp. When the output voltage reaches
K1*1.25V, the Soft Start loop is switched off
and the main loop takes over.
Fault management is controlled either
through power-on-reset (POR) or R_DS(ON)
sense over current protection. Should an
over current condition occur, the SP6122
will completely “lock-up” and turn the PFET
switch off. The only way to recover will be to
either cycle the ENABLE pin or V_CC. A Fault
flag output (FFLAG) has been included to
either signal the upstream circuitry or to
engage a hiccup mode that will restart the
SP6122. Tying FFLAG to ENABLE allows
the controller to restart without assistance.
Lastly, the SP6122 includes a powerful 4Ω
PFET driver stage designed to drive a PFET
associated with high speed converter de-
signs in the 1 A – 5 A range.
THEORY OF OPERATION
Enable
Low quiescent mode or “Sleep Mode” is
initiated by pulling the ENABLE pin below
650mV. The ENABLE pin has an internal
4µA pull-up current and does not require
any external interface for normal operation.
If the ENABLE pin is driven from a voltage
source, the voltage must be above 1.45V in
order to guarantee proper “awake” opera-
tion. Assuming that V_CC is above about
2.9V, the SP6122 transitions from “Sleep
Mode” to “Awake Mode” in about 20µs –
30µs and from “Awake Mode” to “Sleep
Mode” in a few microseconds. SP6122 qui-
escent current in sleep mode is 5µA typical.
During Sleep Mode, the PFET switch is
turned off, the internal SS voltage is held
low and the FFLAG pin is high impedance.
Low Current Operation
If over current fault protection is not needed,
the SP6122 offers two options to lower its
quiescent current. By grounding both I_SET
and I_SENSE pins, the circuitry responsible for
over current detection is turned off. This
option results in a saving of about 50µA in
quiescent current. Option two requires that
I_SET is grounded and ISENSE is greater
than 1.3V. This option put the SP6122 in a
low performance mode that cuts the operat-
ing frequency roughly in half and slows
down critical comparators in the main loop.
Option two can result in additional saving of
100µA bringing the total quiescent current
to only 150µA (typ).
Power On Reset (POR)
The POR command is given every time the
bandgap reference is started. The internal
1.25 V reference is compared against a 1V
NFET threshold. When the reference is below
the threshold, FAULT and RUN latches are
reset, the internal SS voltage is discharged
and the PFET switch is “off”. The SP6122 is
allowed to begin a soft start cycle when the
Rev. 7/16/03
SP6122 Low Voltage, Micro 8, PFET, Buck Controller
6
© Copyright 2003 Sipex Corporation