SP331 Datasheet, PDF (8/13 Pages) Sipex Corporation – Programmable RS-232/RS-485 Transceiver

FUNCTION TABLE FOR SELECT PINS
A BC D
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
MODE
RS-232
RS-232
RS-232
RS-232
FUNCTION
All four RS-232 drivers active
All four RS-232 drivers tri-state
All four RS-232 drivers tri-state
RS-232 (4ch) Loopback
0
1
0
0
1
0
0
1
1
0
1
1
0 RS-232/RS-485 T1 and T2 active RS-232; T3 tri-state RS-485
1 RS-232/RS-485 T1 and T2 tri-state RS-232; T3 active RS-485
0 RS-232/RS-485 T1 and T2 active RS-232; T3 tri-state RS-485
1 RS-232/RS-485 RS-232 (2ch) / RS-485 (1ch) Loopback
1
0
0
1
0
0
1
0
1
1
0
1
0 RS-485/RS-232 T1 active RS-485; T3 and T4 active RS-232
1 RS-485/RS-232 T1 tr-state RS-485; T3 active RS-232; T4 active RS232
0 RS-485/RS-232 All RS-485 and RS-232 drivers tri-state
1 RS-485/RS-232 RS-485 (1ch) / RS-232 (2ch) Loopback
1
1
0
0
RS-485
T1 and T3 active RS-485
1
1
0
1
RS-485
T1 tri-state RS-485; T3 active RS-485
1
1
1
0
RS-485
T1 active RS-485; T3 tri-state RS-485
1
1
1
1
RS-485
RS-485 (2ch) Loopback
Table 1. Mode Function Table. (Refer to Control Logic Confirmations for Block Diagrams)
THEORY OF OPERATION
The SP331 is made up of four separate circuit
blocks — the charge pump, drivers, receivers,
and decoder. Each of these circuit blocks is
described in more detail below.
Charge–Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 10V
power supplies. Figure 15(a) shows the
waveform found on the positive side of capcitor
C2, and Figure 15(b) shows the negative side of
capcitor C2. There is a free–running oscillator
that controls the four phases of the voltage
shifting. A description of each phase follows.
Phase 1
— V_SS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are
then switched
transferred to
Ction₂^{i–gt.iraoSlluiynncdcehaaCnrdg}₂₊^{ecdihsatorcgo+en5noVenc.} tCCe¹d^l+–
is
is
to
+5V, the voltage potential across capacitor C₂
is now 10V.
Phase 2
— V_SS transfer — Phase two of the clock con-
nects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to ground, and transfers the generated –l0V to
C₃. Simultaneously, the positive side of capaci-
tor C ₁ is switched to +5V and the negative side
is connected to ground.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –5V in the negative
terminal of C₁, which
side of capacitor C₂.
is applied
Since C₂₊
to
is
the negative
at +5V, the
voltage potential across C₂ is l0V.
Phase 4
— V_DD transfer — The fourth phase of the
clock connects the negative terminal of C₂ to
ground and transfers the generated l0V across
C₂ to C₄, the V_DD storage capacitor. Again,
Date: 03-04-05
Programmable Dual RS-232/RS-485 Transceiver
8
© Copyright 2005 Sipex Corporation