SP690SEN-L Datasheet, PDF (6/20 Pages) Sipex Corporation – 3.0V/3.3V Low Power Microprocessor Supervisory with Battery Switch-Over

PINOUT
VOUT 1
8 V_BATTERY
VCC
2 ^SP690T/S/R 7 RESET / RESET*
SP802T/S/R
GND 3 SP804T/S/R _{6 WDI}
SP805T/S/R
PFI 4
5 PFO
*SP804T/S/R and SP805T/S/R only
PIN ASSIGNMENTS
Pin 1 —V_OUT — Output Supply Voltage for
CMOS RAM. When V_CC is above the
reset threshold, V_OUT connects to V_CC
through a P-channel MOSFET switch.
When V_CC falls below the V_SW and
V_BATTERY, V_BATTERY connects to V_OUT.
Connect to V_CC if no battery is used.
Pin 2 — V_CC — +5V Supply Input
Pin 3 — GND — Ground reference for all
signals
Pin 4 — PFI — Power-Fail Comparator Input.
When PFI is less than 1.25V or when V_CC
falls below the V_SW, PFO goes LOW,
otherwise PFO remains HIGH. Connect
to GND if unused.
Pin 5 — PFO — Power-Fail Comparator
Output. Leave open if unused.
Pin 6 — WDI — Watchdog Input. If WDI
remains HIGH or LOW for 1.6 seconds,
the internal watchdog timer triggers a
reset. The internal watchdog timer clears
when reset is asserted or WDI sees a
rising or falling edge. The watchdog
function cannot be disabled.
Pin 7 for SP690_/802_ only — Active-LOW
Reset Output. — Whenever RESET is
triggered by a watchdog timeout, it goes
LOW for 200ms. It stays LOW whenever
V_CC is below the reset threshold and re-
mains LOW for 200ms after V_CC rises
above the reset threshold or when the
watchdog triggers a reset.
Pin 7 for SP804_/805_ only — Active-HIGH
Open-Drain Reset Output. — The
inverse operation of RESET.
Pin 8 — V_BATTERY — Backup-Battery Input.
When V_CC falls below V_SW and V_BATTERY,
V_OUT switchesfrom V_CC to V_BATTERY.
When V_CC rises above the reset threshold,
V_OUT reconnects to V_CC. V_BATTERY may
exceed V_CC. Connect to V_CC if no battery
is used.
SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
6
© 2006 Sipex Corporation