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SP6681 Datasheet, PDF (6/10 Pages) Sipex Corporation – High Efficiency Boost Charge Pump Regulator
4) The Clock Phase Control accepts the clock
and mode control generated by the Clock Manager
and the Charge Pump Switch Configuration
Control. This block then provides several clock
phases going to the Drivers block.
5) The VOUT Control regulates the Clock Phase
Control to ensure VOUT is regulated to 5.0V.
6) The Drivers block drives the clock phase
information to the gates of the large pump
transistors.
7) The Charge Pump Switch block contains the
large transistors that transfer charge to the fly
and load capacitors.
In normal operation of the device VINis connected
between +2.7 and 5.5V. Refer to Figure 2 for a
typical application circuit. When no clock is
present (CLK is floating or near ground) the
device is in shutdown and the output is connected
to the input. This shutdown feature will work
either in start up or after the device is pumping.
Once a clock is present, the band gap is activated,
but only if VIN > 2.3V. Otherwise the device
remains in shutdown mode. Once the reference
voltage is stable, the device begins the pumping
operation.
If VIN < 3.70V, the device is configured as a
doubler. However, as the output reaches 5.0V,
the doubler action is truncated.
If VIN is above 3.70V, the device is reconfigured
and multiplies the input by a factor of 1.5. This
mode reduces the current drawn from the supply
and hence increases the power efficiency. As the
output reaches 5.0V, the charge transfer to the
load capacitor is truncated.
APPLICATION INFORMATION
Refer to Figure 3 for a typical SIM card
application circuit with the SP6681.
Oscillator Control
The external clock frequency required to drive
the internal charge pump oscillator is 32.768kHz
(nominal) at the CLK pin. When there is no
clock signal present at the CLK pin, the SP6681
device is in a low-power shutdown mode.
C/4 and Cx8 are two control lines for the internal
charge pump oscillator. When the C/4 control
line is forced to a logic high and the Cx8 control
line is at a low, the internal charge pump oscillator
is set to 8.192kHz. When both the C/4 and Cx8
control lines are at a logic low, the internal
charge pump oscillator is set to the input clock
signal, 32.768kHz. When the C/4 control line is
forced to a logic high, the internal charge pump
oscillator is set to 262.14kHz.
5.0V
VOUT
COUT = 2.2µF
2.7V to 5.5V
VIN
CIN = 4.7µF
CF1 = 2.2µF
Frequency
Control
Inputs
1
CF1P 2
3
C/4 4
Cx8 5
10 CF2P
9 CF1N
SP6681 8 GND
7 CF2N
6 CLK
CF2 = 2.2µF
Input Clock
Figure 2. Typical Application for the SP6681
Rev:A Date: 11/20/03
SP6681 High Efficiency Boost Charge Pump Regulator
6
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