SP6681 Datasheet, PDF (5/10 Pages) Sipex Corporation – High Efficiency Boost Charge Pump Regulator

DESCRIPTION
The SP6681 device is a regulated CMOS charge
pump voltage converter that can be used to
convert a +2.7V to +5.5V input voltage to a
nominal +5.0V output. These devices are ideal
for cellular phone designs involving battery-
powered and/or board level voltage conversion
applications.
An external clock signal with a frequency of
32.768kHz nominal is required for device
operation. A designer can set the SP6681 device
to operate at 3 different charge pump frequencies:
8.192kHz (f / 4), 32.768kHz (f x 1), and
INPUT
INPUT
262.14kHz (f_INPUT x 8). The three frequencies
correspond to three nominal load current ranges:
2mA, 20mA, and 50mA, respectively. The
SP6681 device optimizes for high power
efficiency with a low quiescent current of 175µA
at 8.198kHz, 230µA at 32.768kHz, and 800µA
at 262.14kHz. When there is no external clock
signal input, the device is in a low-power
shutdown mode drawing 4.4µA (typical) current.
The SP6681 device is ideal for designs using
+3.6V lithium ion batteries such as cell phones,
PDAs, medical instruments, and other portable
equipment. For designs involving power sources
above +2.7V up to +5.5V, the internal charge
pump switch architecture dynamically selects an
operational mode that optimizes efficiency. The
SP6681 device regulates the maximum output
voltage to +5.0V.
THEORY OF OPERATION
There are seven major circuit blocks for the
SP6681 device. Refer to Figure 1.
1) The Voltage Reference contains a band gap
and other circuits that provide the proper current
biases and voltage references used in the other
blocks.
2) The Clock Manager accepts the digital input
voltage levels (including the input clock) and
translates them to V_CC and 0V. It also determines
if a clock is present in which case the device is
powered up. If the CLK input is left floating or
pulled near ground, the device shuts down and
V is shorted to V . The worst case digital low
IN
OUT
is 0.4V and the worst case digital high is 1.3V.
This block contains a synthesizer that generates
the internal pump clock which runs at the
frequency controlled with the C/4 and Cx8 logic
pins.
3) The Charge Pump Switch Configuration
Control determines the pump configuration
depending upon V_IN as described earlier and
programs the Clock Phase Control. For an input
supply voltage from +2.7V to +3.7V, an X2
doubling architecture is enabled. This mode
requires one flying capacitor and one output
capacitor. For an input supply voltage greater
than +3.7V up to +5.5V, an X1.5 multiplier
architecture is enabled. This mode requires two
flying capacitors and one output capacitor.
V_{IN 3}
CLK 6
C/4 4
Cx8 5
Voltage
Reference
Clock
Manager
Charge Pump Switch
Configuration Control
Clock Phase
Reference
VOUT
Control
SP6681
Drivers
8
GND
CF1P
CF1N
CF2P
Charge
Pump CF2N
Switches
VOUT
CF1
CF2
COUT
Figure 1. Internal Block Diagram of the SP6681
Rev:A Date: 11/20/03
SP6681 High Efficiency Boost Charge Pump Regulator
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© Copyright 2002 Sipex Corporation