SP6330 Datasheet, PDF (5/13 Pages) Sipex Corporation – Quad μPower Supervisory Circuits with Manual Reset & Watchdog

Pin #
1
2
3
4
5
6
7
8
PIN DESCRIPTION
Name
V1
V2
MRIB
V3
V4
GND
WDI
RST/RSTB
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
Input for the third supply voltage. Trip threshold is 0.5V.
Input for the fourth supply voltage. Trip threshold is 0.5V.
Common ground reference pin.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
5
© Copyright 2006 Sipex Corporation