SP207E Datasheet, PDF (5/16 Pages) Sipex Corporation – +5V High Performance RS232 Transceivers

FEATURES
As in the original RS-232 multi-channel
products, the SP207E Series multi–channel
RS-232 line transceivers provide a variety of
configurations to fit most communication
needs, especially those applications where +12V
is not available. All models in this Series feature
low–power CMOS construction and SIPEX–
proprietary on-board charge pump circuitry to
generate the +10V RS-232 voltage levels. The
ability to use 0.1µF charge pump capacitors
saves board space and reduces circuit cost.
Different models within the Series provide
different driver/receiver combinations to
match any application requirement.
The SP211 and SP213E models feature a low–
power shutdown mode, which reduces power
supply drain to 1µA. The SP213E includes a
Wake-Up function which keeps two receivers
active in the shutdown mode, unless disabled by
the EN pin.
The family is available in 28–pin SO (wide) and
SSOP (shrink) small outline packages. Devices
can be specified for commercial (0°C to +70°C)
and industrial/extended (–40°C to +85°C)
operating temperatures.
THEORY OF OPERATION
The SP207E Series devices are made up of
three basic circuit blocks — 1) transmitter/
driver, 2) receiver and 3) the SIPEX–
proprietary charge pump. Each model within
the Series incorporates variations of these
circuits to achieve the desired configuration
and performance.
Charge–Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external capacitors,
but uses a four–phase voltage shifting technique
to attain symmetrical 10V power supplies.
Figure 3a shows the waveform found on the
positive side of capcitor C₂, and Figure 3b
shows the negative side of capcitor C₂. There is
a free–running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V_SS charge storage —During this phase of the
clock cycle, the positive side of capacitors C₁
and C₂ are initially charged to +5V. C_l+ is then
switched to ground and the charge in C_1– is
transferred to C ^–. Since C ⁺ is connected to
2
2
+5V, the voltage potential across capacitor C is
2
now 10V.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to ground, and transfers the generated –l0V to
C₃. Simultaneously, the positive side of
capacitor C ₁ is switched to +5V and the negative
side is connected to ground.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –5V in the negative
terminal of C₁, which is applied to the negative
side of capacitor C . Since C ⁺ is at +5V, the
2
2
voltage potential across C is l0V.
2
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 1. Charge Pump — Phase 1
SP207EDS/09
SP207E Series High Performance Transceivers
5
© Copyright 2000 Sipex Corporation