SP509 Datasheet, PDF (23/29 Pages) Sipex Corporation – Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors

Since both V⁺ and V^- are separately generated
from V ; in a no-load condition V⁺ and V^- will
CC
be symmetrical. Older charge pump approaches
that generate V^- from V⁺ will show a decrease in
the magnitude of V^- compared to V⁺ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 1µF with a 16V breakdown voltage
rating.
TERM_OFF FUNCTION
The SP509 contains a TERM_OFF pin that
disables all three receiver input termination
networks regardless of mode. This allows the
device to be used in monitor mode applications
typically found in networking test equipment.
The TERM_OFF pin internally contains a
pull-down device with an impedance of over
500kΩ, which will default in a “ON” condition
during power-up if V.35 receivers are used. The
individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
LOOPBACK FUNCTION
The SP509 contains a LOOPBACK pin that
invokes a loopback path. This loopback path is
illustrated in Figure 52. LOOPBACK has an
internal pull-up resistor that defaults to normal
mode during power up or if the pin is left floating.
During loopback, the driver output and receiver
input characteristics will still adhere to its
appropriate specifications.
DECODER AND D_LATCH FUNCTION
The SP509 contains a D_LATCH pin that latches
the data into the D0, D1, and D2 decoder inputs.
If tied to a logic LOW (“0”), the latch is
transparent, allowing the data at the decoder
inputs to propagate through and program
the SP509 accordingly. If tied to a logic
HIGH(“1”), the latch locks out the data and
prevents the mode from changing until this pin
is brought to a logic LOW.
There are internal pull-up devices on D0, D1,
and D2, which allow the device to be in
SHUTDOWN mode (“111”) upon power up.
However , if the device is powered -up with the
D_LATCH at a logic HIGH, the decoder state of
the SP509 will be undefined.
ESD TOLERANCE
The SP509 device incorporates ruggedized ESD
cells on all driver output and receiver input
pins. The ESD structure is improved over our
previous family for more rugged applications
and environments sensitive to electrostatic
discharges and associated transients.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Sipex’s previous multi-protocol
serial transceiver IC’s the drivers and receivers
have been designed to meet all the requirements
to NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy. The SP509 is also
tested in-house at Sipex and adheres to all the
NET1/2 physical layer testing and the ITU Series
V specifications before shipment. Please note
that although the SP509 , as with its predecessors,
adhere to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for details.
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
23
© Copyright 2004 Sipex Corporation