SP509 Datasheet, PDF (22/29 Pages) Sipex Corporation – Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors

The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors and V35RGND
output. The V35RGND is usually grounded. The
receiver itself is identical to the V.11 receiver.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
1Mbps and are used in RS-449/V.36, E1A-530,
E1A-530A and X.21 modes as Category II signals
as indicated by their corresponding specifications.
All receivers include an enable/disable line for
disabling the receiver output allowing convenient
half-duplex configurations. The enable pins will
either enable or disable the output of the receivers
according to the appropriate active logic
illustrated on Figure 47. The receiver’s enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of the
receiver, that enables the receiver upon power up
if the enable lines are left floating. During disabled
conditions, the receiver outputs will be at a high
impedance state. If the receiver is disabled any
associated termination is also disconnected from
the inputs.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5kΩ pull-down resistors on the inputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
CHARGE PUMP
The charge pump is a Sipex-patented design
(5,306,954) and uses a unique approach compared
to older less-efficient designs. The charge pump
still requires four external capacitors, but uses
four-phase voltage shifting technique to attain
symmetrical power supplies. The charge pump
V
DD
and
V_SS
outputs
are
regulated
to
+5.8V
and
-5.8V, respectively. There is a free-running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
Phase 1
__V_SS charge storage ——During this phase of
the clock cycle, the positive side of capacitors C₁
and C₂ are initially charged to V_CC. C+ is then
switched to ground and the charge in C₁- is
transferred to C₂-. Since C₂+ is connected to V_CC,
the voltage potential across capacitor C₂ is now
2_XV_CC.
Phase 2
—V transfer —Phase two of the clock connects
SS
the negative terminal of C₂ to the V_SS storage
capacitor and the positive terminal of C to
2
ground, and transfers the negative generated
voltage to C₃. This generated voltage is regulated
to –5.8V. Simultaneously, the positive side of
the capacitor C₁ is switched to V_CC and the
negative side is connected to ground.
Phase 3
—V_DD charge storage —The third phase of the
clock is identical to the first phase—the charge
transferred in C₁ produces –V_CC in the negative
terminal of C which is applied to the negative
1
side of the capacitor C . Since C + is at V , the
2
2
CC
voltage potential across C is 2 V .
2
X CC
Phase 4
—V_DD transfer —The fourth phase of the clock
connects the negative terminal of C₂ to ground,
and transfers the generated 5.8V across C₂ to C₄,
the V_DD storage capacitor. This voltage is
regulated to +5.8V. At the regulated voltage, the
internal oscillator is disabled and simultaneously
with this, the positive side of capacitor C₁ is
switched to V_CC and the negative side is connected
to ground, and the cycle begins again. The charge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
22
© Copyright 2004 Sipex Corporation