SP707EN-L Datasheet, PDF (12/18 Pages) Sipex Corporation – Low Power Microprocessor Supervisory Circuits

sensitivity to high-frequency noise on the
line being monitored. RESET can be used to
monitor voltages other than the +5V V_CC
line. Connect PFO to MR to initiate a RESET
pulse when PFI drops below 1.25V. Figure 17
shows the SP705/706/707/708 configured to
assert RESET when the +5V supply falls below
the RESET threshold, or when the +12V supply
falls below approximately 11V.
Monitoring a Negative Voltage Supply
The power-fail comparator can also monitor a
negative supply rail, shown in Figure 18. When
the negative rail is good (a negative voltage of
large magnitude), PFO is LOW. By adding the
resistors and transistor as shown, a HIGH PFO
triggers RESET. As long as PFO remains HIGH,
the SP705-708/813L/813M will keep RESET
asserted (where RESET = LOW and RESET =
HIGH). Note that this circuit's accuracy de-
pends on the PFI threshold tolerance, the V_CC
line, and the resistors.
Interfacing to mPs with Bidirectional
RESET Pins
µPs with bidirectional RESET pins, such as the
Motorola 68HC11 series, can contend with the
SP705/706/707/708 RESET output. If, for
example, the RESET output is driven HIGH and
the µP wants to pull it LOW, indeterminate
logic levels may result. To correct this, connect
a 4.7KΩ resistor between the RESET output and
the µP reset I/O, as shown if Figure 19. Buffer
the RESET output to other system components.
+5V
10100KKΩ
MR
2N3904
PFO
11000KKΩΩ
to µP
RESET
VCC
R1
PFI
R2
V-
GND
R1 ₌ 5.0 - 1.25 _{, VTRIP < 0}
R2 1.25 - VTRIP
+5V
MR
0V
V-
+5V
PFO
0V
V-
VTRIP
0V
Figure 18. Monitoring a Negative Voltage Supply
Buffered RESET connects to System Components
+5V
+5V
VCC
VCC
RESET
µP
RESET
4.7KΩ
GND
GND
Figure 19. Interfacing to Microprocessors with
Bidirectional RESET I/O for the SP705/706/707/708
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
12
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