SP43701 Datasheet, PDF (9/12 Pages) SIPAT Co,Ltd – 50 Ω RF Digital Attenuator

SP43701
Product Specification
Figure 20. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
ADD[2:0]
P/S
SI
CLK
T_DISU
VALID
T_ASU
T_PSSU
D[0]
T_SISU
T_SIH
LE
D[1]
T_CLKL
D[2]
D[3]
D[4]
D[5]
T_CLKH
D[6]
A[0]
A[1]
A[2]
DO[6:0]
T_DIH
T_AH
T_PSH
T_LESU
T_LEPW
T_PD
VALID
Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
DI[6:0]
LE
DO[6:0]
T_PSSU
VALID
T_DISU
T_PSH
T_DIH
T_LEPW
VALID
T_DIPD
T_PD
Table 11. Serial Interface AC Characteristics
V_DD = 3.3 or 5.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK Serial clock frequency
-
10 MHz
TCLKH Serial clock HIGH time
30
-
ns
TCLKL Serial clock LOW time
30
-
ns
TLESU
Last serial clock rising edge
setup time to Latch Enable
rising edge
10
-
ns
TLEPW Latch Enable min. pulse width 30
-
ns
TSISU Serial data setup time
10
-
ns
TSIH
Serial data hold time
10
-
ns
TDISU Parallel data setup time
100
-
ns
TDIH Parallel data hold time
100
-
ns
TASU Address setup time
100
-
ns
TAH
Address hold time
100
-
ns
TPSSU Parallel/Serial setup time
100
-
ns
TPSH Parallel/Serial hold time
100
-
ns
TPD
Digital register delay (internal)
-
10 ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
Table 12. Parallel and Direct Interface AC
Characteristics
V_DD = 3.3 or 5.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
TLEPW
Latch Enable minimum
pulse width
30
-
ns
TDISU
Parallel data setup time
100 -
ns
TDIH
Parallel data hold time
100 -
ns
TPSSU
Parallel/Serial setup time
100 -
ns
TPSIH
TPD
TDIPD
Parallel/Serial hold time
100 -
ns
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
-
10 ns
-
5
ns
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