SP4304 Datasheet, PDF (8/10 Pages) SIPAT Co,Ltd – 75 Ω RF Digital Attenuator

Figure 18. Serial Interface Timing Diagram
LE
Clock
Data
MSB
t_SDSUP
t_SDHLD
LSB
t_LESUP
t_LEPW
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C16:C0.5
t_PDSUP
t_LEPW
t_PDHLD
SP4304
Product Specification
Table 7. 6-Bit Attenuator Serial Programming
Register Map
B5
B4
B3
B2
B1
B0
C16
C8
C4
C2
C1
C0.5
↑
MSB (first in)
↑
LSB (last in)
Table 8. Serial Interface AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
fClk
Parameter
Serial data clock
frequency (Note 1)
Min Max Unit
10
MHz
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tLESUP
LE set-up time after last
clock falling edge
10
ns
tLEPW
LE minimum pulse width
30
ns
tSDSUP
Serial data set-up time
before clock rising edge
10
ns
tSDHLD
Serial data hold time
after clock falling edge
10
ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
Table 9. Parallel Interface AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
tLEPW
LE minimum pulse width
10
ns
tPDSUP
Data set-up time before
rising edge of LE
10
ns
tPDHLD
Data hold time after
falling edge of LE
10
ns
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