U632H64 Datasheet, PDF (9/15 Pages) List of Unclassifed Manufacturers – PowerStore 8K x 8 nvSRAM

Software Controlled STORE/RECALL Cycle^{t, u, v, w} (E = HIGH after STORE initiation)
Ai
E
DQi
Output
t_cR (29)
ADDRESS 1
t_{su(A)SR (33)}
t_w(E)SR
(34)
(35) ^th(A)SR
High Impedance _VALID
t_{cR (29)}
ADDRESS 6
t_w(E)SR
(35) th(A)SR
(34)
t_{dis(E) (5)}
(33)
t_su(A)SR
t_d(E)S(31) t_d(E)R (32)
VALID
t_{dis(E)SR (30)}
Software Controlled STORE/RECALL Cycle^{t, u, v, w} (E = LOW after STORE initiation)
Ai
E
DQi
Output
t_cR (29)
ADDRESS 1
t_w(E)SR
(33)
t_su(A)SR
(34)
(35) th(A)SR
High Impedance _VALID
ADDRESS 6
t_h(A)SR (35)
(33)
t_su(A)SR
t_d(E)S (31)
t_{d(E)R (32)}
VALID
t_{dis(E)SR (30)}
U632H64
u: If the chip enable pulse width is less then t_a(E) (see READ cycle) but greater than or equal to t_w(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U632H64 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
August 15, 2006
STK Control #ML0047
9
Rev 1.1