U631H16 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – SOFTSTORE 2K X 8 NVSRAM

Read Cycle 1: Ai-controlled (during Read cycle: E ⁼ G ⁼ V_IL, W = V_IH)^f
Ai
DQi
Output
t_cR (1)
Address Valid
t_{a(A) (2)}
Previous Data Valid
t_{v(A) (9)}
Output Data Valid
U631H16
Read Cycle 2: G-, E-controlled (during Read cycle: W = V_IH)^g
Ai
E
G
DQi
Output
I_CC
t_{cR (1)}
Address Valid
t_{a(A) (2)}
t_{a(E) (3)}
t_{en(E) (7)}
t_{a(G) (4)}
High Impedance
ACTIVE
STANDBY
t_{en(G) (8)}
t_PU (10)
t_PD (11)
t_{dis(E) (5)}
t_{dis(G) (6)}
Output Data Valid
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z^{h, i}
23 W HIGH to Output in Low-Z
Symbol
25
35
45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
t_AVAV
t_AVAV
t_cW 25
35
45
ns
t_WLWH
t_w(W) 20
30
35
ns
t_WLEH t_su(W) 20
30
35
ns
t_AVWL t_AVEL
t_su(A)
0
0
0
ns
t_AVWH t_AVEH t_su(A-WH) 20
30
35
ns
t_ELWH
t_su(E) 20
30
35
ns
t_ELEH
t_w(E) 20
30
35
ns
t_DVWH t_DVEH t_su(D) 12
18
20
ns
t_WHDX t_EHDX
t_h(D)
0
0
0
ns
t_WHAX t_EHAX
t_h(A)
0
0
0
ns
t_WLQZ
t_dis(W)
10
13
15 ns
t_WHQX
t_en(W) 5
5
5
ns
March 31, 2006
STK Control #ML0042
5
Rev 1.0