STK14D88 Datasheet, PDF (5/19 Pages) List of Unclassifed Manufacturers – 32K x 8 AutoStore nvSRAM CMOS Nonvolatile Static RAM

SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
1
2
t_AVAVc
3
t_AVQVd
4
5
t_AXQXd
6
7
8
9
10
11
t_ELQV
t_AVAVc
t_AVQVd
t_GLQV
t_AXQXd
t_ELQX
t_EHQZe
t_GLQX
t_GHQZe
t_ELICCHb
t_EHICCLb
t_ACS
t_RC
t_AA
t_OE
t_OH
t_LZ
t_HZ
t_OLZ
t_OHZ
t_PA
t_PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured ± 200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
STK14D88
STK14D88-25
MIN MAX
25
25
25
12
3
3
10
0
10
0
25
STK14D88-35
MIN MAX
35
35
35
15
3
3
13
0
13
0
35
STK14D88-45
MIN MAX
45
45
45
20
3
3
15
0
15
0
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM READ CYCLE #1: Address Controlled^c,d,f
ADDRESS
DQ (DATA OUT)
5
t_AXQX
2
t_AVAV
3
t_AVQV
DATA VALID
SRAM READ CYCLE #2: E Controlled^c,f
ADDRESS
E
6
t_ELQX
2
t_AVAV
1
t_ELQV
G
DQ (DATA OUT)
I_CC
8
t_GLQX
4
t_GLQV
10
t_ELICCH
STANDBY
ACTIVE
11
t_EHICCL
7
t_EHQZ
9
t_GHQZ
DATA VALID
Document Control #ML0033 Rev 1.7
5
February 2007