U630H16XS Datasheet, PDF (11/16 Pages) Simtek Corporation – HardStore 2K x 8 nvSRAM Die

Test Configuration for Functional Check
U630H16XS
5V
V_CCt
A0
A1
A2
DQ0
A3
DQ1
480
V_IH
A4
A5
DQ2
A6
DQ3
A7
DQ4
A8
DQ5
V_IL
A9
A10
DQ6
DQ7
V_O
NE
E
W
G
V_SS
30 pF ^s
255
s: In measurement of t_dis-times and t_en-times the capacitance is 5 pF.
t: Between V_CC and V_SS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitance^e
Conditions
Symbol
Min.
Max.
Input Capacitance
V_CC = 5.0 V
C_I
8
V_I
= V_SS
f
= 1 MHz
Output Capacitance
T_a = 25 °C
C_O
7
All pads not under test must be connected with ground by capacitors.
Ordering Code
Example
Type
bare die
U630H16 XS C 25
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
A = -40 to 125 °C (only 35 ns)
Access Time
25 = 25 ns
35 = 35 ns
45 = 45 ns
Unit
pF
pF
Bonding Instructions
The U630H16XS has 30 relevant bond pads and 4 additional pads.
The 4 additional pads must not be bonded.
Refer to the bond pad location and identification table for a complete list of bond pads and coordinates.
It is mandatory to use a bond wire on each VCC and two bond wires on VSS bond pad for noise immunity.
The backside of the die is connected to VCC and can be contacted with the substrate in case of the same potential.
The pad VBND has to be connected with VCC in order to enable the HardStore mode of the chip.
March 31, 2006
STK Control #ML0039
11
Rev 1.0