U630H16XS Datasheet, PDF (1/16 Pages) Simtek Corporation – HardStore 2K x 8 nvSRAM Die

Obsolete - Not Recommended for New Designs
U630H16XS
HardStore 2K x 8 nvSRAM Die
Features
Description
• High-performance CMOS non-
volatile static RAM 2048 x 8 bits
• 25, 35 and 45 ns Access Times
• 12, 20 and 25 ns Output Enable
Access Times
• Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 10⁶ STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Hardware RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Unlimited SRAM Read and Write
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 90000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
The U630H16 has two separate
modes of operation: SRAM mode
and non-volatile mode, determined
by the state of the NE pad.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
non-volatile operation, data is
transferred in parallel from SRAM
to EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H16 is a fast static RAM
(25, 35, 45 ns), with a non-volatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent non-volatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pad.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with non-volatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the non-vola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The non-volatile data can be
recalled an unlimited number of
times.
The chips are tested with a
restricted wafer probe program
at room temperature only. Unte-
sted parameters are marked with
a number sign (#).
Pad Configuration
Pad Description
A5 A6 A7 NE VCC VBND W HSB A8 A9
A4
W
A3
G
A2
A10
A1
E
A0 DQ0 DQ1 DQ2 VSS VCC DQ3 DQ4 DQ5 DQ6 DQ7
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
NE
VCC
VSS
VBND
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
HardStore type enable
March 31, 2006
STK Control #ML0039
1
Rev 1.0