SII0680A Datasheet, PDF (46/124 Pages) Silicon image – PCI to IDE/ATA

SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9. Register Definitions
This section describes the registers within the SiI 0680A PCI-ATA host controller ASIC.
9.1 PCI Configuration Space
The PCI Configuration Space registers define the operation of the SiI 0680A on the PCI bus. These registers are accessible
only when the SiI 0680A detects a Configuration Read or Write operation, with its IDSEL asserted, on the 32-bit PCI bus.
Table 9-1, outlines the PCI Configuration space for the SiI 0680A.
Address
Offset
00_H
04_H
08_H
0C_H
10_H
14_H
18_H
1C_H
20_H
24_H
28_H
2C_H
30_H
34_H
38_H
3C_H
40_H
44_H
48_H
4C_H
50_H
Register Name
31
15
16
00
Device ID (0680h)
Vendor ID (1095h)
PCI Status
PCI Command
PCI Class Code
Revision ID
BIST
Header Type
Latency Timer
Cache Line Size
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Reserved
Subsystem ID (0680h)
Subsystem Vendor ID (1095h)
Expansion ROM Base Address
Reserved
Capabilities Ptr
Reserved
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
Reserved
Configuration
Software Data Register
Reserved
Reserved
Reserved
Access
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R
R/W
R/W
R/W
R/W
-
-
-
Table 9-1: PCI-680 PCI Configuration Space
© 2006 Silicon Image, Inc.
46
SiI-DS-0069-C