SC63C0316 Datasheet, PDF (10/24 Pages) Silan Microelectronics Joint-stock – AUDIO CONTROL SYSTEM WITH BUILTIN

SC63C0316
TABLE1. Interrupt request flag conditions and priorities
Interrupt Internal/
source External
Condition for IRQx flag setting
INTB
I
Reference time interval signal from basic timer
INT4
E
Both rising and falling edges detected at INT4
INT0
E
Rising or falling edge detected at INT0 pin
INT1
E
Rising or falling edge detected at INT1 pin
INTS
Completion signal for serial transmit-and-receive or
I
receive-only operation
INTT0
I
Signals for TCNT0 and TREF0 retgisters match
INTCE
E
When falling edge is detected at CE pin
INTIF
I
When gate closes
INT2*
Rising edge detected at INT2 or else a falling edge is
E
detected at any of the KS0-KS3 pins
INTW
I
Time interval of 0.5s or 3.19ms
* The quasi-interrupt INT2 is only used for testing incoming signals.
Interrupt
priority
1
1
2
3
Request flag
name
IRQB
IRQ4
IRQ0
IRQ1
4
IRQS
5
IRQT0
6
IRQCE
7
IRQIF
--
IRQ2
--
IRQW
INTERRUPT ENABLE FLAGS (IEx)
IEx flags, when set to "1", enable specific interrupt requests to be serviced. When the interrupt request flag is
set to "1", an interrupt will not be serviced until its corresponding IEx flag is also enabled. The IPR register
contains a global disable bit, IME, which disables all interrupt at once.
INTERRUPT PRIORITY
Each interrupt source can also be individually programmed to high levels by modifying the IPR register. When
IS1 = 0 and IS0 = 1, a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another
low-priority interrupt.
If you clear the interrupt status flags (IS1 and IS0) to "0" in a interrupt service routine, a high-priority interrupt
can be interrupted by low-priority interrupt (multi-level interrupt). Before the IPR can be modified by 4-bit write
instructions, all interrupts must first be disabled by a DI instruction.
When all interrupts are low priority (the lower three bits of the IPR register are "0"), the interrupt requested first
will have high priority. Therefore, the first-requested interrupt cannot be superseded by any other interrupt.
If two or more interrupt requests are received simultaneously, the priority level is determined according to the
standard interrupt priorities, where the default priority is assigned by hardware when the lower three IPR bits =
"0".
In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the
high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is
started.
Table 2. Interrupt Priority Register Settings
IPR.2
0
IPR.1
0
IPR.0
0
Result of IPR Bit Setting
Process all interrupt requests at default priority settings.
0
0
1
INTB and INT4 at highest priority.
0
1
0
INT0 at highest priority.
0
1
1
INT1 at highest priority.
1
0
0
INTS at highest priority.
1
0
1
INTT0 at highest priority.
1
1
0
INTCE at highest priority.
1
1
1
INTIF at highest priority.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2004.08.03
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