SI5100-EVB Datasheet, PDF (8/48 Pages) Silicon Laboratories – Evaluation Board Set for Si5100 and Si5110 OC-48/STM-16 SONET/SDH TRANSCEIVERS

Si5100/Si5110-EVB
Table 4. Si5110 Daughter Card Setup
Header—Pin Signal Name
Line Loopback
JP1—20
JP1—23
BWSEL0
BWSEL1
11
(for widest CMU loop
bandwidth)
JP1—17
REFSEL
high
JP1—14 TXCLKDSBL
low
JP1—11
TXMSBSEL
low
JP1—8
TXSQLCH_N
high
JP1—5
SLICEMODE
low
JP1—2
RXMSBSEL
low
Note: Jump the VDD_IO selection jumper toward the 3.3 V side.
Asynchronous TX/RX
11
(for widest CMU loop
bandwidth)
high
low
low
high
low
low
Diagnostic Loopback
11
(for widest CMU loop
bandwidth)
high
low
low
high
low
low
8
Preliminary Rev. 0.5