SI5100-EVB Datasheet, PDF (7/48 Pages) Silicon Laboratories – Evaluation Board Set for Si5100 and Si5110 OC-48/STM-16 SONET/SDH TRANSCEIVERS

Si5100/Si5110-EVB
Both the motherboard and daughter card are placed in line loopback mode before shipment to customers.
Table 1. Loopback Motherboard Setup
Header—Pin
JP10—2
JP1—14
JP1—11
JP1—8
JP1—5
JP1—2
JP2—5
JP2—2
JP3—8
JP3—5
JP3—2
JP7—5
JP7—2
JP6—4
Signal Name
Voltage Select
RXCLK1DSBL_N
LTR_N
RXSQLCH_N
RXCLK2DIV_N
RXCLK2DSBL_N
TXREFRATE
TXRESET_N
DLBK_N
LLBK_N
LPTM_N
RXREFRATE
RXRESET_N
FIFORST_N
Line Loopback
3.3 V
high
high
low
don’t care
don’t care
high
high
high
low (enables line loopback)
high
open
high
tie to FIFOERR
Asynchronous TX/RX
3.3 V
high
high
high
don’t care
don’t care
high
high
high
high
high
open
high
tie to FIFOERR
Table 2. Full-Duplex Motherboard Setup
Header—Pin
JP8—2
JP1—14
JP1—11
JP1—8
JP1—5
JP1—2
JP2—5
JP2—2
JP3—8
JP3—5
JP3—2
JP7—5
JP7—2
JP6—4
Signal Name
Voltage Select
RXCLK1DSBL_N
LTR_N
RXSQLCH_N
RXCLK2DIV_N
RXCLK2DSBL_N
REFRATE
RESET_N
DLBK_N
LLBK_N
LPTM_N
Si5530 REFRATE
Si5530 RESET_N
FIFORST_N
Line Loopback
3.3 V
high
high
low
don’t care
don’t care
high
high
high
low (enables line loopback)
high
open
high
tie to FIFOERR
Asynchronous TX/RX
3.3 V
high
high
high
don’t care
don’t care
high
high
high
high
high
open
high
tie to FIFOERR
Diagnostic Loopback
3.3 V
high
high
high
don’t care
don’t care
high
high
low
high
high
open
high
tie to FIFOERR
Table 3. Si5100 Daughter Card Setup
Header—Pin Signal Name
Line Loopback
JP1—20
JP1—23
BWSEL0
BWSEL1
11
(for widest CMU loop
bandwidth)
JP1—17
REFSEL
high
JP1—14
MODE16
high
JP1—11 TXCLKDSBL
low
JP1—8
TXMSBSEL
low
JP1—5
TXSQLCH_N
high
JP1—2
RXMSBSEL
low
Note: Jump the VDD_IO selection jumper toward the 3.3 V side.
Asynchronous TX/RX
11
(for widest CMU loop
bandwidth)
high
high
low
low
high
low
Diagnostic Loopback
11
(for widest CMU loop
bandwidth)
high
high
low
low
high
low
Preliminary Rev. 0.5
7