SI51218 Datasheet, PDF (7/13 Pages) Silicon Laboratories – THREE OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR

2. Design Considerations
2.1. Typical Application Schematic
VDD
Si51218
0.1µF
CL1
CL2
VDD
VDDO
XOUT
CLKOUT3
Si51218
XIN
CLKOUT2
CLKOUT1
VSS
0.1µF
10µF
Dotted line shows the optional termination resistors
2.2. Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on the pins 1 and
8. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin. In addition, a 10 µF capacitor should be placed between VDD and VSS.
Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. DO NOT USE higher overtone
crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula:
CL1 = CL2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the Si51218 pin capacitance (4pF)
Cp is the parasitic capacitance of the PCB traces.
Example: If a crystal with CL=12 pF specification is used and Cp=1 pF (parasitic PCB capacitance on PCB), 19 pF
external capacitors from pins XIN (pin 3) and XOUT (Pin 2) to VSS are required. Users must verify Cp value.
Rev. 1.0
7