SI51218 Datasheet, PDF (5/13 Pages) Silicon Laboratories – THREE OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR

Si51218
Table 2. AC Electrical Specifications
(V_DD=3.3 V ± 10% or V_DD=2.5 V ± 5%, T_A=0 to 70 ^oC)
Parameter
Input Frequency Range
Input Frequency Range
Output Frequency Range
Frequency Accuracy
Output Duty Cycle
Input Duty Cycle
Output Rise Time
Output Fall Time
Period Jitter
Period Jitter
Cycle-to-Cycle Jitter
Power-up Time
Symbol
F_IN1
F_IN2
F_OUT
F_ACC
DC_OUT
DC_IN
t_r
t_f
PJ₁
PJ₂
CCJ
t_PU
Test Condition
Crystal input
Reference clock Input
Configuration dependent
Measured at V_DD/2
CLKIN, CLKOUT through PLL
CLKOUT1/2/3 in MHz range
C_L=15 pF, 20 to 80%
CLKOUT1/2/3 in MHz range
C_L=15 pF, 20 to 80%
CLKOUT1/2/3 in MHz range,
V_DD=V_DDO=3.3 V, CL=15 pF
CLKOUT1/3 at 32.768KHz,
V_DD=V_DDO=3.3 V, CL=15 pF
CLKOUT1/2/3, in MHz range
V_DD=V_DDO=3.3 V, CL=15 pF
Time from 0.9 V_DD to valid fre-
quencies at all clock outputs
Min
Typ
8
—
3
—
0.032768 —
—
0
45
50
30
50
—
1
—
1
—
150^*
—
1500^*
—
100^*
—
1.2
Output Enable Time
t_OE
Time from OE raising edge to
—
15
active at outputs (asynchronous)
Output Disable Time
t_OD
Time from OE falling edge to
—
15
active at outputs (asynchronous)
*Note: Jitter performance depends on configuration and programming parameters.
Max
48
166
200
—
55
70
3.0
3.0
—
—
—
5.0
—
—
Unit
MHz
MHz
MHz
ppm
%
%
ns
ns
ps
ps
ps
ms
ns
ns
Rev. 1.0
5