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SI510 Datasheet, PDF (7/26 Pages) Silicon Laboratories – CRYSTAL OSCILLATOR 100 kHZ TO 250 MHZ | |||
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Si510/511
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = â40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples1
â
â
1.3
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples1
â
â
11
ps
Phase Jitter
(RMS)
ÏJ
1.875 MHz to 20 MHz integration
â
0.31
0.5
ps
bandwidth2 (brickwall)
Phase Noise,
156.25 MHz
12 kHz to 20 MHz integration band-
â
width2 (brickwall)
ÏN
100 Hz
â
1 kHz
â
0.8
â86
â109
1.0
ps
â
dBc/Hz
â
dBc/Hz
10 kHz
â
â116
â
dBc/Hz
100 kHz
â
â123
â
dBc/Hz
Additive RMS
Jitter Due to
External Power
Supply Noise3
JPSR
1 MHz
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
â
â136
â
dBc/Hz
â
3.0
â
ps
â
3.5
â
ps
â
3.5
â
ps
Spurious
SPR
1 MHz sinusoidal noise
LVPECL output, 156.25 MHz,
offset>10 kHz
â
3.5
â
ps
â
â75
â
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
Rev. 1.1
7
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