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SI510 Datasheet, PDF (6/26 Pages) Silicon Laboratories – CRYSTAL OSCILLATOR 100 kHZ TO 250 MHZ | |||
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Si510/511
Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = â40 to +85 oC
Parameter
CMOS Output Logic
High
CMOS Output Logic
Low
CMOS Output Logic
High Drive
Symbol
VOH
VOL
IOH
Test Condition
3.3 V
2.5 V
Min
0.85 x VDD
â
â8
â6
1.8 V
â4
CMOS Output Logic
Low Drive
IOL
3.3 V
8
2.5 V
6
CMOS Output Rise/Fall
Time
(20 to 80% VDD)
LVPECL/HCSL Output
Rise/Fall Time
(20 to 80% VDD)
LVDS Output Rise/Fall
Time (20 to 80% VDD)
LVPECL Output
Common Mode
LVPECL Output Swing
LVDS Output Common
Mode
LVDS Output Swing
HCSL Output Common
Mode
HCSL Output Swing
Duty Cycle
TR/TF
TR/TF
1.8 V
0.1 to 212.5 MHz,
CL = 15 pF
0.1 to 212.5 MHz,
CL = no load
TR/TF
VOC
50 ï to VDD â 2 V,
single-ended
VO
50 ï to VDD â 2 V,
single-ended
VOC
100 ï line-line
VDD = 3.3/2.5 V
100 ï line-line, VDD = 1.8 V
VO Single-ended, 100 ïï differential
termination
VOC
50 ïï to ground
VO
Single-ended
DC
All formats
4
â
â
â
â
â
0.55
1.13
0.83
0.25
0.35
0.58
48
Typ
â
â
â
â
â
â
â
â
0.8
0.6
â
â
VDD â
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
Max
Unit
â
V
0.15 x VDD V
â
mA
â
mA
â
mA
â
mA
â
mA
â
mA
1.2
ns
0.9
ns
565
ps
800
ps
â
V
0.90
1.33
VPPSE
V
1.00
0.45
0.42
0.85
52
V
VPPSE
V
VPPSE
%
6
Rev. 1.1
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