SI5020C-BA Datasheet, PDF (7/14 Pages) Silicon Laboratories – Si5020 MICRO PCB WITH S3050 FOOTPRINT

Si5020C-BA
Functional Description
The Si5020C-BA is a micro PCB that adapts the Si5020
device to meet the footprint and essential functionality
of the AMCC S3050 device. It allows substitution of the
Si5020 device in systems designed for the S3050. The
Si5020C-BA board is comprised of the Si5020 CDR
device and support circuitry for voltage regulation,
initiation of calibration, and lock detect signal polarity
inversion. A schematic diagram for the Si5020C-BA is
given in the "Si5020C-BA Schematic Diagram" on page
4.
Si5020 CDR Device
Please refer to the Si5020 data sheet for detailed
operation and performance data for the Si5020 CDR
device.
Voltage Regulator Circuit
To account for the power supply requirement
differences between the S3050 and the Si5020, a low-
dropout linear voltage regulator is used to regulate the
Si5020C-BA board’s 5 V supply input down to the 2.5 V
supply used for the Si5020.
Generation of the PWRDN/CAL Signal
To achieve optimal jitter performance, the Si5020 device
provides an internal self-calibration capability. Self-
calibration optimizes loop gain parameters within the
Si5020 DSPLL. Self-calibration is initiated by the falling
edge of the Si5020 device PWRDN/CAL input signal.
On the Si5020C-BA board, the Si5020 PWRDN/CAL
signal is driven from the voltage regulator POK output
signal through series capacitor C2. This circuit is
identical to one described within Silicon Laboratories’
application note AN42: “Controlling DSPLL™ Self-
calibration for the Si5020/5018/5010 CDR Devices and
Si531x Clock Multiplier/Regenerator Devices”
Rate Select Inputs
The RATESEL pins are used to set operating data rates
for the Si5020C-BA. These pins set internal frequency
dividers in the Si5020 device. The RATESEL pin
settings for each data rate are given in Table 4
Table 4. Multi-Rate Configuration
RATESEL
[1:0]
SONET/
SDH
Gigabit OC-48 w/
Ethernet 15/14 FEC
00
2.488 Gbps
—
2.67 Gbps
10
1.244 Gbps 1.25 Gbps
—
01
622.08 Mbps
—
—
11
155.52 Mbps
—
—
Relative to the Si5020, the S3050 RATESEL pins are
reversed such that RATESEL0 on the Si5020
corresponds to RATESEL1 on the S3050. This
swapped mapping is handled on the Si5020C-BA such
that the RATESEL inputs on the S3050-BA board match
those of the S3050 device.
Lock Detect Output
Lock detection is performed by the Si5020 device. The
LOL signal from the Si5020 device has an inverted
polarity relative to that of the S3050. An inverting/level-
shifting buffer is utilized on the Si5020C-BA to provide a
TTL compatible LOCKDET output from the board that
matches the S3050 output signal polarity. This signal
will go high when the Si5020C-BA locks to the incoming
serial data.
Reference Clock Input
The reference clock inputs (REFCLKP/N) provide
coarse frequency information to the Si5020. This
frequency information is used to identify the incoming
serial data frequency and provide lock detection.
The supported frequencies for OC-48/12/3 are 155.52,
77.76, and 19.44 MHz. These frequencies are
automatically detected within the Si5020 and no digital
control inputs are required for clock frequency selection.
The REFCLKP/N inputs are internally biased to an input
common mode voltage of 2.0 V and provide 100 Ω line-
to-line termination. AC coupling is recommended as the
simplest coupling approach. (See "Typical Application
Schematic" on page 6.) Full details on the REFCLKP/N
pins can be found in the Si5020 data sheet REFCLK±
pin descriptions.
Rev. 1.0
7