EFM32LG395 Datasheet, PDF (67/82 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Alternate
Functionality
0
U0_RX
PF7
U0_TX
PF6
U1_RX
PC13
U1_TX
PC12
US0_CLK
US0_CS
PE12
PE13
US0_RX
PE11
1
PE1
PE0
PF11
PF10
PE5
PE4
LOCATION
2
3
4
PA4 PC15
PA3 PC14
PB10 PE3
PB9 PE2
PC9 PC15 PB13
PC8 PC14 PB14
5
PB13
PB14
PE6
PC10 PE12 PB8
PC1
US0_TX
US1_CLK
US1_CS
US1_RX
PE10
PB7
PB8
PC1
PE7
PC11 PE13 PB7
PC0
PD2
PF0
PD3
PF1
PD1
PD6
US1_TX
PC0
US2_CLK
PC4
US2_CS
PC5
US2_RX
PC3
PD0
PD7
PB5
PB6
PB4
US2_TX
PC2
PB3
USB_DM
USB_DMPU
USB_DP
USB_ID
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VREGO
PF10
PD2
PF11
PF12
USB_VBUS
PF5
USB_VREGI
USB_VREGO
6
Description
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half
duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half
duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32LG395 is shown in Table 4.3 (p. 68) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
2014-06-13 - EFM32LG395FXX - d0114_Rev1.30
67
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