EFM32LG942 Datasheet, PDF (62/78 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Alternate
Functionality
0
US0_CLK
PE12
US0_CS
PE13
US0_RX
PE11
1
PE5
PE4
LOCATION
2
3
4
PB13
PB14
5
PB13
PB14
PE6
PE12 PB8
US0_TX
US1_CLK
US1_CS
US1_RX
PE10
PB7
PB8
PE7
PE13 PB7
PD2
PF0
PD3
PF1
PD1
PD6
US1_TX
US2_CLK
PC4
US2_CS
PC5
US2_RX
PD0
PD7
PB5
PB6
PB4
US2_TX
PB3
USB_DM
USB_DMPU
USB_DP
USB_ID
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VREGO
PF10
PD2
PF11
PF12
USB_VBUS
PF5
USB_VREGI
USB_VREGO
6
Description
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32LG942 is shown in Table 4.3 (p. 63) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
2014-06-13 - EFM32LG942FXX - d0121_Rev1.30
62
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