EFM32HG108 Datasheet, PDF (6/53 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

Preliminary
2.2 Configuration Summary
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The features of the EFM32HG108 is a subset of the feature set described in the EFM32HG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M0+
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
USART0
USART1
LEUART0
TIMER0
TIMER1
TIMER2
RTC
PCNT0
ACMP0
VCMP
GPIO
Configuration
Pin Connections
Full configuration
NA
Full configuration
DBG_SWCLK, DBG_SWDIO,
Full configuration
NA
Full configuration
NA
Full configuration
NA
Full configuration
NA
Full configuration
CMU_OUT0, CMU_OUT1
Full configuration
NA
Full configuration
NA
Full configuration
I2C0_SDA, I2C0_SCL
Full configuration with IrDA and I2S
US0_TX, US0_RX. US0_CLK, US0_CS
Full configuration with I2S and IrDA
US1_TX, US1_RX, US1_CLK, US1_CS
Full configuration
LEU0_TX, LEU0_RX
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
Full configuration
TIM1_CC[2:0]
Full configuration
TIM2_CC[2:0]
Full configuration
NA
Full configuration, 16-bit count register PCNT0_S[1:0]
Full configuration
ACMP0_CH[1:0], ACMP0_O
Full configuration
NA
17 pins
Available pins are shown in
Table 4.3 (p. 40)
2.3 Memory Map
The EFM32HG108 memory map is shown in Figure 2.2 (p. 7) , with RAM and Flash sizes for the
largest memory configuration.
2015-05-06 - EFM32HG108FXX - _Rev0.91
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